//------------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
//            (C) COPYRIGHT 2012 ARM Limited.
//                ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//------------------------------------------------------------------------------
// Version and Release Control Information:
//
// File Revision       : 126202
// File Date           :  2012-03-02 11:28:07 +0000 (Fri, 02 Mar 2012)
// Release Information : PL401-r0p1-00eac0
//------------------------------------------------------------------------------
// Purpose : Top Level structural file that integrates all the modules required
//           for the AXI bus matrix 
//
// Key Configuration Details:
//
//  * Name                        : switch2
//  * Number of Slave Interfaces  : 2
//  * Number of Master Interfaces : 9
//  * Data Width (Bits)           : 32
//  * Protocol                    : axi4
//
// Notes on port naming conventions:
//
//  All AXI point to point connections can be considered a
//  MasterInterface - SlaveInterface connection.
//
//  The AXI ports on the NIC400 AXI BM are named as follows:
//
//  *_m<n> suffix to denote a MasterInterface (connect to external AXI slave)
//  *_s<n> suffix to denote a SlaveInterface  (conenct to external AXI master)
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
// Module Declaration
//------------------------------------------------------------------------------

module nic400_switch2_ysyx_rv32
  (
    ////master Interface Port axi_m_0

    //AW Channel
    awid_axi_m_0,
    awaddr_axi_m_0,
    awlen_axi_m_0,
    awsize_axi_m_0,
    awburst_axi_m_0,
    awlock_axi_m_0,
    awcache_axi_m_0,
    awprot_axi_m_0,
    awregion_axi_m_0,
    awvalid_axi_m_0,
    awvalid_vect_axi_m_0,
    awready_axi_m_0,

    //W Channel
    wdata_axi_m_0,
    wstrb_axi_m_0,
    wlast_axi_m_0,
    wvalid_axi_m_0,
    wready_axi_m_0,

    //B Channel
    bid_axi_m_0,
    bresp_axi_m_0,
    bvalid_axi_m_0,
    bready_axi_m_0,

    //AR Channel
    arid_axi_m_0,
    araddr_axi_m_0,
    arlen_axi_m_0,
    arsize_axi_m_0,
    arburst_axi_m_0,
    arlock_axi_m_0,
    arcache_axi_m_0,
    arprot_axi_m_0,
    arregion_axi_m_0,
    arvalid_axi_m_0,
    arvalid_vect_axi_m_0,
    arready_axi_m_0,

    //R Channel
    rid_axi_m_0,
    rdata_axi_m_0,
    rresp_axi_m_0,
    rlast_axi_m_0,
    rvalid_axi_m_0,
    rready_axi_m_0,

    //QV signals
    aw_qv_axi_m_0,
    ar_qv_axi_m_0,

    ////master Interface Port axi_m_1

    //AW Channel
    awid_axi_m_1,
    awaddr_axi_m_1,
    awlen_axi_m_1,
    awsize_axi_m_1,
    awburst_axi_m_1,
    awlock_axi_m_1,
    awcache_axi_m_1,
    awprot_axi_m_1,
    awregion_axi_m_1,
    awvalid_axi_m_1,
    awvalid_vect_axi_m_1,
    awready_axi_m_1,

    //W Channel
    wdata_axi_m_1,
    wstrb_axi_m_1,
    wlast_axi_m_1,
    wvalid_axi_m_1,
    wready_axi_m_1,

    //B Channel
    bid_axi_m_1,
    bresp_axi_m_1,
    bvalid_axi_m_1,
    bready_axi_m_1,

    //AR Channel
    arid_axi_m_1,
    araddr_axi_m_1,
    arlen_axi_m_1,
    arsize_axi_m_1,
    arburst_axi_m_1,
    arlock_axi_m_1,
    arcache_axi_m_1,
    arprot_axi_m_1,
    arregion_axi_m_1,
    arvalid_axi_m_1,
    arvalid_vect_axi_m_1,
    arready_axi_m_1,

    //R Channel
    rid_axi_m_1,
    rdata_axi_m_1,
    rresp_axi_m_1,
    rlast_axi_m_1,
    rvalid_axi_m_1,
    rready_axi_m_1,

    //QV signals
    aw_qv_axi_m_1,
    ar_qv_axi_m_1,

    ////slave Interface Port axi_s_0

    //AW Channel
    awid_axi_s_0,
    awaddr_axi_s_0,
    awlen_axi_s_0,
    awsize_axi_s_0,
    awburst_axi_s_0,
    awlock_axi_s_0,
    awcache_axi_s_0,
    awprot_axi_s_0,
    awregion_axi_s_0,
    awvalid_axi_s_0,
    awvalid_vect_axi_s_0,
    awready_axi_s_0,

    //W Channel
    wdata_axi_s_0,
    wstrb_axi_s_0,
    wlast_axi_s_0,
    wvalid_axi_s_0,
    wready_axi_s_0,

    //B Channel
    bid_axi_s_0,
    bresp_axi_s_0,
    bvalid_axi_s_0,
    bready_axi_s_0,

    //AR Channel
    arid_axi_s_0,
    araddr_axi_s_0,
    arlen_axi_s_0,
    arsize_axi_s_0,
    arburst_axi_s_0,
    arlock_axi_s_0,
    arcache_axi_s_0,
    arprot_axi_s_0,
    arregion_axi_s_0,
    arvalid_axi_s_0,
    arvalid_vect_axi_s_0,
    arready_axi_s_0,

    //R Channel
    rid_axi_s_0,
    rdata_axi_s_0,
    rresp_axi_s_0,
    rlast_axi_s_0,
    rvalid_axi_s_0,
    rready_axi_s_0,

    //QV signals
    aw_qv_axi_s_0,
    ar_qv_axi_s_0,

    ////master Interface Port axi_m_2

    //AW Channel
    awid_axi_m_2,
    awaddr_axi_m_2,
    awlen_axi_m_2,
    awsize_axi_m_2,
    awburst_axi_m_2,
    awlock_axi_m_2,
    awcache_axi_m_2,
    awprot_axi_m_2,
    awregion_axi_m_2,
    awvalid_axi_m_2,
    awvalid_vect_axi_m_2,
    awready_axi_m_2,

    //W Channel
    wdata_axi_m_2,
    wstrb_axi_m_2,
    wlast_axi_m_2,
    wvalid_axi_m_2,
    wready_axi_m_2,

    //B Channel
    bid_axi_m_2,
    bresp_axi_m_2,
    bvalid_axi_m_2,
    bready_axi_m_2,

    //AR Channel
    arid_axi_m_2,
    araddr_axi_m_2,
    arlen_axi_m_2,
    arsize_axi_m_2,
    arburst_axi_m_2,
    arlock_axi_m_2,
    arcache_axi_m_2,
    arprot_axi_m_2,
    arregion_axi_m_2,
    arvalid_axi_m_2,
    arvalid_vect_axi_m_2,
    arready_axi_m_2,

    //R Channel
    rid_axi_m_2,
    rdata_axi_m_2,
    rresp_axi_m_2,
    rlast_axi_m_2,
    rvalid_axi_m_2,
    rready_axi_m_2,

    //QV signals
    aw_qv_axi_m_2,
    ar_qv_axi_m_2,

    ////master Interface Port axi_m_5

    //AW Channel
    awid_axi_m_5,
    awaddr_axi_m_5,
    awlen_axi_m_5,
    awsize_axi_m_5,
    awburst_axi_m_5,
    awlock_axi_m_5,
    awcache_axi_m_5,
    awprot_axi_m_5,
    awregion_axi_m_5,
    awvalid_axi_m_5,
    awvalid_vect_axi_m_5,
    awready_axi_m_5,

    //W Channel
    wdata_axi_m_5,
    wstrb_axi_m_5,
    wlast_axi_m_5,
    wvalid_axi_m_5,
    wready_axi_m_5,

    //B Channel
    bid_axi_m_5,
    bresp_axi_m_5,
    bvalid_axi_m_5,
    bready_axi_m_5,

    //AR Channel
    arid_axi_m_5,
    araddr_axi_m_5,
    arlen_axi_m_5,
    arsize_axi_m_5,
    arburst_axi_m_5,
    arlock_axi_m_5,
    arcache_axi_m_5,
    arprot_axi_m_5,
    arregion_axi_m_5,
    arvalid_axi_m_5,
    arvalid_vect_axi_m_5,
    arready_axi_m_5,

    //R Channel
    rid_axi_m_5,
    rdata_axi_m_5,
    rresp_axi_m_5,
    rlast_axi_m_5,
    rvalid_axi_m_5,
    rready_axi_m_5,

    //QV signals
    aw_qv_axi_m_5,
    ar_qv_axi_m_5,

    ////master Interface Port axi_m_6

    //AW Channel
    awid_axi_m_6,
    awaddr_axi_m_6,
    awlen_axi_m_6,
    awsize_axi_m_6,
    awburst_axi_m_6,
    awlock_axi_m_6,
    awcache_axi_m_6,
    awprot_axi_m_6,
    awregion_axi_m_6,
    awvalid_axi_m_6,
    awvalid_vect_axi_m_6,
    awready_axi_m_6,

    //W Channel
    wdata_axi_m_6,
    wstrb_axi_m_6,
    wlast_axi_m_6,
    wvalid_axi_m_6,
    wready_axi_m_6,

    //B Channel
    bid_axi_m_6,
    bresp_axi_m_6,
    bvalid_axi_m_6,
    bready_axi_m_6,

    //AR Channel
    arid_axi_m_6,
    araddr_axi_m_6,
    arlen_axi_m_6,
    arsize_axi_m_6,
    arburst_axi_m_6,
    arlock_axi_m_6,
    arcache_axi_m_6,
    arprot_axi_m_6,
    arregion_axi_m_6,
    arvalid_axi_m_6,
    arvalid_vect_axi_m_6,
    arready_axi_m_6,

    //R Channel
    rid_axi_m_6,
    rdata_axi_m_6,
    rresp_axi_m_6,
    rlast_axi_m_6,
    rvalid_axi_m_6,
    rready_axi_m_6,

    //QV signals
    aw_qv_axi_m_6,
    ar_qv_axi_m_6,

    ////slave Interface Port axi_s_1

    //AW Channel
    awid_axi_s_1,
    awaddr_axi_s_1,
    awlen_axi_s_1,
    awsize_axi_s_1,
    awburst_axi_s_1,
    awlock_axi_s_1,
    awcache_axi_s_1,
    awprot_axi_s_1,
    awregion_axi_s_1,
    awvalid_axi_s_1,
    awvalid_vect_axi_s_1,
    awready_axi_s_1,

    //W Channel
    wdata_axi_s_1,
    wstrb_axi_s_1,
    wlast_axi_s_1,
    wvalid_axi_s_1,
    wready_axi_s_1,

    //B Channel
    bid_axi_s_1,
    bresp_axi_s_1,
    bvalid_axi_s_1,
    bready_axi_s_1,

    //AR Channel
    arid_axi_s_1,
    araddr_axi_s_1,
    arlen_axi_s_1,
    arsize_axi_s_1,
    arburst_axi_s_1,
    arlock_axi_s_1,
    arcache_axi_s_1,
    arprot_axi_s_1,
    arregion_axi_s_1,
    arvalid_axi_s_1,
    arvalid_vect_axi_s_1,
    arready_axi_s_1,

    //R Channel
    rid_axi_s_1,
    rdata_axi_s_1,
    rresp_axi_s_1,
    rlast_axi_s_1,
    rvalid_axi_s_1,
    rready_axi_s_1,

    //QV signals
    aw_qv_axi_s_1,
    ar_qv_axi_s_1,

    ////master Interface Port axi_m_7

    //AW Channel
    awid_axi_m_7,
    awaddr_axi_m_7,
    awlen_axi_m_7,
    awsize_axi_m_7,
    awburst_axi_m_7,
    awlock_axi_m_7,
    awcache_axi_m_7,
    awprot_axi_m_7,
    awregion_axi_m_7,
    awvalid_axi_m_7,
    awvalid_vect_axi_m_7,
    awready_axi_m_7,

    //W Channel
    wdata_axi_m_7,
    wstrb_axi_m_7,
    wlast_axi_m_7,
    wvalid_axi_m_7,
    wready_axi_m_7,

    //B Channel
    bid_axi_m_7,
    bresp_axi_m_7,
    bvalid_axi_m_7,
    bready_axi_m_7,

    //AR Channel
    arid_axi_m_7,
    araddr_axi_m_7,
    arlen_axi_m_7,
    arsize_axi_m_7,
    arburst_axi_m_7,
    arlock_axi_m_7,
    arcache_axi_m_7,
    arprot_axi_m_7,
    arregion_axi_m_7,
    arvalid_axi_m_7,
    arvalid_vect_axi_m_7,
    arready_axi_m_7,

    //R Channel
    rid_axi_m_7,
    rdata_axi_m_7,
    rresp_axi_m_7,
    rlast_axi_m_7,
    rvalid_axi_m_7,
    rready_axi_m_7,

    //QV signals
    aw_qv_axi_m_7,
    ar_qv_axi_m_7,

    ////master Interface Port axi_m_8

    //AW Channel
    awid_axi_m_8,
    awaddr_axi_m_8,
    awlen_axi_m_8,
    awsize_axi_m_8,
    awburst_axi_m_8,
    awlock_axi_m_8,
    awcache_axi_m_8,
    awprot_axi_m_8,
    awregion_axi_m_8,
    awvalid_axi_m_8,
    awvalid_vect_axi_m_8,
    awready_axi_m_8,

    //W Channel
    wdata_axi_m_8,
    wstrb_axi_m_8,
    wlast_axi_m_8,
    wvalid_axi_m_8,
    wready_axi_m_8,

    //B Channel
    bid_axi_m_8,
    bresp_axi_m_8,
    bvalid_axi_m_8,
    bready_axi_m_8,

    //AR Channel
    arid_axi_m_8,
    araddr_axi_m_8,
    arlen_axi_m_8,
    arsize_axi_m_8,
    arburst_axi_m_8,
    arlock_axi_m_8,
    arcache_axi_m_8,
    arprot_axi_m_8,
    arregion_axi_m_8,
    arvalid_axi_m_8,
    arvalid_vect_axi_m_8,
    arready_axi_m_8,

    //R Channel
    rid_axi_m_8,
    rdata_axi_m_8,
    rresp_axi_m_8,
    rlast_axi_m_8,
    rvalid_axi_m_8,
    rready_axi_m_8,

    //QV signals
    aw_qv_axi_m_8,
    ar_qv_axi_m_8,

    ////master Interface Port axi_m_9

    //AW Channel
    awid_axi_m_9,
    awaddr_axi_m_9,
    awlen_axi_m_9,
    awsize_axi_m_9,
    awburst_axi_m_9,
    awlock_axi_m_9,
    awcache_axi_m_9,
    awprot_axi_m_9,
    awregion_axi_m_9,
    awvalid_axi_m_9,
    awvalid_vect_axi_m_9,
    awready_axi_m_9,

    //W Channel
    wdata_axi_m_9,
    wstrb_axi_m_9,
    wlast_axi_m_9,
    wvalid_axi_m_9,
    wready_axi_m_9,

    //B Channel
    bid_axi_m_9,
    bresp_axi_m_9,
    bvalid_axi_m_9,
    bready_axi_m_9,

    //AR Channel
    arid_axi_m_9,
    araddr_axi_m_9,
    arlen_axi_m_9,
    arsize_axi_m_9,
    arburst_axi_m_9,
    arlock_axi_m_9,
    arcache_axi_m_9,
    arprot_axi_m_9,
    arregion_axi_m_9,
    arvalid_axi_m_9,
    arvalid_vect_axi_m_9,
    arready_axi_m_9,

    //R Channel
    rid_axi_m_9,
    rdata_axi_m_9,
    rresp_axi_m_9,
    rlast_axi_m_9,
    rvalid_axi_m_9,
    rready_axi_m_9,

    //QV signals
    aw_qv_axi_m_9,
    ar_qv_axi_m_9,

    ////master Interface Port axi_m_4

    //AW Channel
    awid_axi_m_4,
    awaddr_axi_m_4,
    awlen_axi_m_4,
    awsize_axi_m_4,
    awburst_axi_m_4,
    awlock_axi_m_4,
    awcache_axi_m_4,
    awprot_axi_m_4,
    awregion_axi_m_4,
    awvalid_axi_m_4,
    awvalid_vect_axi_m_4,
    awready_axi_m_4,

    //W Channel
    wdata_axi_m_4,
    wstrb_axi_m_4,
    wlast_axi_m_4,
    wvalid_axi_m_4,
    wready_axi_m_4,

    //B Channel
    bid_axi_m_4,
    bresp_axi_m_4,
    bvalid_axi_m_4,
    bready_axi_m_4,

    //AR Channel
    arid_axi_m_4,
    araddr_axi_m_4,
    arlen_axi_m_4,
    arsize_axi_m_4,
    arburst_axi_m_4,
    arlock_axi_m_4,
    arcache_axi_m_4,
    arprot_axi_m_4,
    arregion_axi_m_4,
    arvalid_axi_m_4,
    arvalid_vect_axi_m_4,
    arready_axi_m_4,

    //R Channel
    rid_axi_m_4,
    rdata_axi_m_4,
    rresp_axi_m_4,
    rlast_axi_m_4,
    rvalid_axi_m_4,
    rready_axi_m_4,

    //QV signals
    aw_qv_axi_m_4,
    ar_qv_axi_m_4,

    //Clock and reset signals
    aclk,
    aresetn

  );

  // ---------------------------------------------------------------------------
  //  parameters
  // ---------------------------------------------------------------------------

  // ---------------------------------------------------------------------------
  //  Port definitions
  // ---------------------------------------------------------------------------
  
  ////master Interface Port axi_m_0


  //AW Channel
  output  [3:0]       awid_axi_m_0;              //write id of axi_m_0 AXI bus AW channel
  output  [31:0]      awaddr_axi_m_0;            //write address of axi_m_0 AXI bus AW channel
  output  [7:0]       awlen_axi_m_0;             //write length field of axi_m_0 AXI bus AW channel
  output  [2:0]       awsize_axi_m_0;            //write size of axi_m_0 AXI bus AW channel
  output  [1:0]       awburst_axi_m_0;           //write burst length of axi_m_0 AXI bus AW channel
  output              awlock_axi_m_0;            //write lock of axi_m_0 AXI bus AW channel
  output  [3:0]       awcache_axi_m_0;           //write cache field of axi_m_0 AXI bus AW channel
  output  [2:0]       awprot_axi_m_0;            //write prot field of axi_m_0 AXI bus AW channel
  output  [3:0]       awregion_axi_m_0;          //write region field of axi_m_0 AXI bus AW channel
  output              awvalid_axi_m_0;           //write valid of axi_m_0 AXI bus AW channel
  output              awvalid_vect_axi_m_0;      //write valid vector of axi_m_0 AXI bus AW Channel
  input               awready_axi_m_0;           //write ready of axi_m_0 AXI bus AW channel

  //W Channel
  output  [31:0]      wdata_axi_m_0;             //write data of axi_m_0 AXI bus W Channel
  output  [3:0]       wstrb_axi_m_0;             //write strobes of axi_m_0 AXI bus W Channel
  output              wlast_axi_m_0;             //write last of axi_m_0 AXI bus W Channel
  output              wvalid_axi_m_0;            //write valid of axi_m_0 AXI bus W Channel
  input               wready_axi_m_0;            //write ready of axi_m_0 AXI bus W Channel

  //B Channel
  input   [3:0]       bid_axi_m_0;               //b response id of axi_m_0 AXI bus B Channel
  input   [1:0]       bresp_axi_m_0;             //b response status of axi_m_0 AXI bus B Channel
  input               bvalid_axi_m_0;            //b response valid of axi_m_0 AXI bus B Channel
  output              bready_axi_m_0;            //b response ready of axi_m_0 AXI bus B Channel

  //AR Channel
  output  [3:0]       arid_axi_m_0;              //read id of axi_m_0 AXI bus AR Channel
  output  [31:0]      araddr_axi_m_0;            //read address of axi_m_0 AXI bus AR Channel
  output  [7:0]       arlen_axi_m_0;             //read length of axi_m_0 AXI bus AR Channel
  output  [2:0]       arsize_axi_m_0;            //read size of axi_m_0 AXI bus AR Channel
  output  [1:0]       arburst_axi_m_0;           //read burst length of axi_m_0 AXI bus AR Channel
  output              arlock_axi_m_0;            //read lock of axi_m_0 AXI bus AR Channel
  output  [3:0]       arcache_axi_m_0;           //read cache field of axi_m_0 AXI bus AR Channel
  output  [2:0]       arprot_axi_m_0;            //read prot field of axi_m_0 AXI bus AR Channel
  output  [3:0]       arregion_axi_m_0;          //read region field of axi_m_0 AXI bus AR channel
  output              arvalid_axi_m_0;           //read valid of axi_m_0 AXI bus AR Channel
  output              arvalid_vect_axi_m_0;      //read valid vector of axi_m_0 AXI bus AR Channel
  input               arready_axi_m_0;           //read ready of axi_m_0 AXI bus AR Channel

  //R Channel
  input   [3:0]       rid_axi_m_0;               //read id of axi_m_0 AXI bus R Channel
  input   [31:0]      rdata_axi_m_0;             //read data of axi_m_0 AXI bus R Channel
  input   [1:0]       rresp_axi_m_0;             //read response status of axi_m_0 AXI bus R Channel
  input               rlast_axi_m_0;             //read last of axi_m_0 AXI bus R Channel
  input               rvalid_axi_m_0;            //read valid of axi_m_0 AXI bus R Channel
  output              rready_axi_m_0;            //read ready of axi_m_0 AXI bus R Channel

  //QV signals
  output  [3:0]       aw_qv_axi_m_0;             //Quality Value axi_m_0 AXI bus AW Channel
  output  [3:0]       ar_qv_axi_m_0;             //Quality value axi_m_0 AXI bus AR Channel

  ////master Interface Port axi_m_1


  //AW Channel
  output  [3:0]       awid_axi_m_1;              //write id of axi_m_1 AXI bus AW channel
  output  [31:0]      awaddr_axi_m_1;            //write address of axi_m_1 AXI bus AW channel
  output  [7:0]       awlen_axi_m_1;             //write length field of axi_m_1 AXI bus AW channel
  output  [2:0]       awsize_axi_m_1;            //write size of axi_m_1 AXI bus AW channel
  output  [1:0]       awburst_axi_m_1;           //write burst length of axi_m_1 AXI bus AW channel
  output              awlock_axi_m_1;            //write lock of axi_m_1 AXI bus AW channel
  output  [3:0]       awcache_axi_m_1;           //write cache field of axi_m_1 AXI bus AW channel
  output  [2:0]       awprot_axi_m_1;            //write prot field of axi_m_1 AXI bus AW channel
  output  [3:0]       awregion_axi_m_1;          //write region field of axi_m_1 AXI bus AW channel
  output              awvalid_axi_m_1;           //write valid of axi_m_1 AXI bus AW channel
  output              awvalid_vect_axi_m_1;      //write valid vector of axi_m_1 AXI bus AW Channel
  input               awready_axi_m_1;           //write ready of axi_m_1 AXI bus AW channel

  //W Channel
  output  [31:0]      wdata_axi_m_1;             //write data of axi_m_1 AXI bus W Channel
  output  [3:0]       wstrb_axi_m_1;             //write strobes of axi_m_1 AXI bus W Channel
  output              wlast_axi_m_1;             //write last of axi_m_1 AXI bus W Channel
  output              wvalid_axi_m_1;            //write valid of axi_m_1 AXI bus W Channel
  input               wready_axi_m_1;            //write ready of axi_m_1 AXI bus W Channel

  //B Channel
  input   [3:0]       bid_axi_m_1;               //b response id of axi_m_1 AXI bus B Channel
  input   [1:0]       bresp_axi_m_1;             //b response status of axi_m_1 AXI bus B Channel
  input               bvalid_axi_m_1;            //b response valid of axi_m_1 AXI bus B Channel
  output              bready_axi_m_1;            //b response ready of axi_m_1 AXI bus B Channel

  //AR Channel
  output  [3:0]       arid_axi_m_1;              //read id of axi_m_1 AXI bus AR Channel
  output  [31:0]      araddr_axi_m_1;            //read address of axi_m_1 AXI bus AR Channel
  output  [7:0]       arlen_axi_m_1;             //read length of axi_m_1 AXI bus AR Channel
  output  [2:0]       arsize_axi_m_1;            //read size of axi_m_1 AXI bus AR Channel
  output  [1:0]       arburst_axi_m_1;           //read burst length of axi_m_1 AXI bus AR Channel
  output              arlock_axi_m_1;            //read lock of axi_m_1 AXI bus AR Channel
  output  [3:0]       arcache_axi_m_1;           //read cache field of axi_m_1 AXI bus AR Channel
  output  [2:0]       arprot_axi_m_1;            //read prot field of axi_m_1 AXI bus AR Channel
  output  [3:0]       arregion_axi_m_1;          //read region field of axi_m_1 AXI bus AR channel
  output              arvalid_axi_m_1;           //read valid of axi_m_1 AXI bus AR Channel
  output              arvalid_vect_axi_m_1;      //read valid vector of axi_m_1 AXI bus AR Channel
  input               arready_axi_m_1;           //read ready of axi_m_1 AXI bus AR Channel

  //R Channel
  input   [3:0]       rid_axi_m_1;               //read id of axi_m_1 AXI bus R Channel
  input   [31:0]      rdata_axi_m_1;             //read data of axi_m_1 AXI bus R Channel
  input   [1:0]       rresp_axi_m_1;             //read response status of axi_m_1 AXI bus R Channel
  input               rlast_axi_m_1;             //read last of axi_m_1 AXI bus R Channel
  input               rvalid_axi_m_1;            //read valid of axi_m_1 AXI bus R Channel
  output              rready_axi_m_1;            //read ready of axi_m_1 AXI bus R Channel

  //QV signals
  output  [3:0]       aw_qv_axi_m_1;             //Quality Value axi_m_1 AXI bus AW Channel
  output  [3:0]       ar_qv_axi_m_1;             //Quality value axi_m_1 AXI bus AR Channel

  ////slave Interface Port axi_s_0


  //AW Channel
  input   [3:0]       awid_axi_s_0;              //write id of axi_s_0 AXI bus AW channel
  input   [31:0]      awaddr_axi_s_0;            //write address of axi_s_0 AXI bus AW channel
  input   [7:0]       awlen_axi_s_0;             //write length field of axi_s_0 AXI bus AW channel
  input   [2:0]       awsize_axi_s_0;            //write size of axi_s_0 AXI bus AW channel
  input   [1:0]       awburst_axi_s_0;           //write burst length of axi_s_0 AXI bus AW channel
  input               awlock_axi_s_0;            //write lock of axi_s_0 AXI bus AW channel
  input   [3:0]       awcache_axi_s_0;           //write cache field of axi_s_0 AXI bus AW channel
  input   [2:0]       awprot_axi_s_0;            //write prot field of axi_s_0 AXI bus AW channel
  input   [3:0]       awregion_axi_s_0;          //write region field of axi_s_0 AXI bus AW channel
  input               awvalid_axi_s_0;           //write valid of axi_s_0 AXI bus AW channel
  input   [8:0]       awvalid_vect_axi_s_0;      //write valid vector of axi_s_0 AXI bus AW Channel
  output              awready_axi_s_0;           //write ready of axi_s_0 AXI bus AW channel

  //W Channel
  input   [31:0]      wdata_axi_s_0;             //write data of axi_s_0 AXI bus W Channel
  input   [3:0]       wstrb_axi_s_0;             //write strobes of axi_s_0 AXI bus W Channel
  input               wlast_axi_s_0;             //write last of axi_s_0 AXI bus W Channel
  input               wvalid_axi_s_0;            //write valid of axi_s_0 AXI bus W Channel
  output              wready_axi_s_0;            //write ready of axi_s_0 AXI bus W Channel

  //B Channel
  output  [3:0]       bid_axi_s_0;               //b response id of axi_s_0 AXI bus B Channel
  output  [1:0]       bresp_axi_s_0;             //b response status of axi_s_0 AXI bus B Channel
  output              bvalid_axi_s_0;            //b response valid of axi_s_0 AXI bus B Channel
  input               bready_axi_s_0;            //b response ready of axi_s_0 AXI bus B Channel

  //AR Channel
  input   [3:0]       arid_axi_s_0;              //read id of axi_s_0 AXI bus AR Channel
  input   [31:0]      araddr_axi_s_0;            //read address of axi_s_0 AXI bus AR Channel
  input   [7:0]       arlen_axi_s_0;             //read length of axi_s_0 AXI bus AR Channel
  input   [2:0]       arsize_axi_s_0;            //read size of axi_s_0 AXI bus AR Channel
  input   [1:0]       arburst_axi_s_0;           //read burst length of axi_s_0 AXI bus AR Channel
  input               arlock_axi_s_0;            //read lock of axi_s_0 AXI bus AR Channel
  input   [3:0]       arcache_axi_s_0;           //read cache field of axi_s_0 AXI bus AR Channel
  input   [2:0]       arprot_axi_s_0;            //read prot field of axi_s_0 AXI bus AR Channel
  input   [3:0]       arregion_axi_s_0;          //read region field of axi_s_0 AXI bus AR channel
  input               arvalid_axi_s_0;           //read valid of axi_s_0 AXI bus AR Channel
  input   [8:0]       arvalid_vect_axi_s_0;      //read valid vector of axi_s_0 AXI bus AR Channel
  output              arready_axi_s_0;           //read ready of axi_s_0 AXI bus AR Channel

  //R Channel
  output  [3:0]       rid_axi_s_0;               //read id of axi_s_0 AXI bus R Channel
  output  [31:0]      rdata_axi_s_0;             //read data of axi_s_0 AXI bus R Channel
  output  [1:0]       rresp_axi_s_0;             //read response status of axi_s_0 AXI bus R Channel
  output              rlast_axi_s_0;             //read last of axi_s_0 AXI bus R Channel
  output              rvalid_axi_s_0;            //read valid of axi_s_0 AXI bus R Channel
  input               rready_axi_s_0;            //read ready of axi_s_0 AXI bus R Channel

  //QV signals
  input   [3:0]       aw_qv_axi_s_0;             //Quality Value axi_s_0 AXI bus AW Channel
  input   [3:0]       ar_qv_axi_s_0;             //Quality value axi_s_0 AXI bus AR Channel

  ////master Interface Port axi_m_2


  //AW Channel
  output  [3:0]       awid_axi_m_2;              //write id of axi_m_2 AXI bus AW channel
  output  [31:0]      awaddr_axi_m_2;            //write address of axi_m_2 AXI bus AW channel
  output  [7:0]       awlen_axi_m_2;             //write length field of axi_m_2 AXI bus AW channel
  output  [2:0]       awsize_axi_m_2;            //write size of axi_m_2 AXI bus AW channel
  output  [1:0]       awburst_axi_m_2;           //write burst length of axi_m_2 AXI bus AW channel
  output              awlock_axi_m_2;            //write lock of axi_m_2 AXI bus AW channel
  output  [3:0]       awcache_axi_m_2;           //write cache field of axi_m_2 AXI bus AW channel
  output  [2:0]       awprot_axi_m_2;            //write prot field of axi_m_2 AXI bus AW channel
  output  [3:0]       awregion_axi_m_2;          //write region field of axi_m_2 AXI bus AW channel
  output              awvalid_axi_m_2;           //write valid of axi_m_2 AXI bus AW channel
  output              awvalid_vect_axi_m_2;      //write valid vector of axi_m_2 AXI bus AW Channel
  input               awready_axi_m_2;           //write ready of axi_m_2 AXI bus AW channel

  //W Channel
  output  [31:0]      wdata_axi_m_2;             //write data of axi_m_2 AXI bus W Channel
  output  [3:0]       wstrb_axi_m_2;             //write strobes of axi_m_2 AXI bus W Channel
  output              wlast_axi_m_2;             //write last of axi_m_2 AXI bus W Channel
  output              wvalid_axi_m_2;            //write valid of axi_m_2 AXI bus W Channel
  input               wready_axi_m_2;            //write ready of axi_m_2 AXI bus W Channel

  //B Channel
  input   [3:0]       bid_axi_m_2;               //b response id of axi_m_2 AXI bus B Channel
  input   [1:0]       bresp_axi_m_2;             //b response status of axi_m_2 AXI bus B Channel
  input               bvalid_axi_m_2;            //b response valid of axi_m_2 AXI bus B Channel
  output              bready_axi_m_2;            //b response ready of axi_m_2 AXI bus B Channel

  //AR Channel
  output  [3:0]       arid_axi_m_2;              //read id of axi_m_2 AXI bus AR Channel
  output  [31:0]      araddr_axi_m_2;            //read address of axi_m_2 AXI bus AR Channel
  output  [7:0]       arlen_axi_m_2;             //read length of axi_m_2 AXI bus AR Channel
  output  [2:0]       arsize_axi_m_2;            //read size of axi_m_2 AXI bus AR Channel
  output  [1:0]       arburst_axi_m_2;           //read burst length of axi_m_2 AXI bus AR Channel
  output              arlock_axi_m_2;            //read lock of axi_m_2 AXI bus AR Channel
  output  [3:0]       arcache_axi_m_2;           //read cache field of axi_m_2 AXI bus AR Channel
  output  [2:0]       arprot_axi_m_2;            //read prot field of axi_m_2 AXI bus AR Channel
  output  [3:0]       arregion_axi_m_2;          //read region field of axi_m_2 AXI bus AR channel
  output              arvalid_axi_m_2;           //read valid of axi_m_2 AXI bus AR Channel
  output              arvalid_vect_axi_m_2;      //read valid vector of axi_m_2 AXI bus AR Channel
  input               arready_axi_m_2;           //read ready of axi_m_2 AXI bus AR Channel

  //R Channel
  input   [3:0]       rid_axi_m_2;               //read id of axi_m_2 AXI bus R Channel
  input   [31:0]      rdata_axi_m_2;             //read data of axi_m_2 AXI bus R Channel
  input   [1:0]       rresp_axi_m_2;             //read response status of axi_m_2 AXI bus R Channel
  input               rlast_axi_m_2;             //read last of axi_m_2 AXI bus R Channel
  input               rvalid_axi_m_2;            //read valid of axi_m_2 AXI bus R Channel
  output              rready_axi_m_2;            //read ready of axi_m_2 AXI bus R Channel

  //QV signals
  output  [3:0]       aw_qv_axi_m_2;             //Quality Value axi_m_2 AXI bus AW Channel
  output  [3:0]       ar_qv_axi_m_2;             //Quality value axi_m_2 AXI bus AR Channel

  ////master Interface Port axi_m_5


  //AW Channel
  output  [3:0]       awid_axi_m_5;              //write id of axi_m_5 AXI bus AW channel
  output  [31:0]      awaddr_axi_m_5;            //write address of axi_m_5 AXI bus AW channel
  output  [7:0]       awlen_axi_m_5;             //write length field of axi_m_5 AXI bus AW channel
  output  [2:0]       awsize_axi_m_5;            //write size of axi_m_5 AXI bus AW channel
  output  [1:0]       awburst_axi_m_5;           //write burst length of axi_m_5 AXI bus AW channel
  output              awlock_axi_m_5;            //write lock of axi_m_5 AXI bus AW channel
  output  [3:0]       awcache_axi_m_5;           //write cache field of axi_m_5 AXI bus AW channel
  output  [2:0]       awprot_axi_m_5;            //write prot field of axi_m_5 AXI bus AW channel
  output  [3:0]       awregion_axi_m_5;          //write region field of axi_m_5 AXI bus AW channel
  output              awvalid_axi_m_5;           //write valid of axi_m_5 AXI bus AW channel
  output              awvalid_vect_axi_m_5;      //write valid vector of axi_m_5 AXI bus AW Channel
  input               awready_axi_m_5;           //write ready of axi_m_5 AXI bus AW channel

  //W Channel
  output  [31:0]      wdata_axi_m_5;             //write data of axi_m_5 AXI bus W Channel
  output  [3:0]       wstrb_axi_m_5;             //write strobes of axi_m_5 AXI bus W Channel
  output              wlast_axi_m_5;             //write last of axi_m_5 AXI bus W Channel
  output              wvalid_axi_m_5;            //write valid of axi_m_5 AXI bus W Channel
  input               wready_axi_m_5;            //write ready of axi_m_5 AXI bus W Channel

  //B Channel
  input   [3:0]       bid_axi_m_5;               //b response id of axi_m_5 AXI bus B Channel
  input   [1:0]       bresp_axi_m_5;             //b response status of axi_m_5 AXI bus B Channel
  input               bvalid_axi_m_5;            //b response valid of axi_m_5 AXI bus B Channel
  output              bready_axi_m_5;            //b response ready of axi_m_5 AXI bus B Channel

  //AR Channel
  output  [3:0]       arid_axi_m_5;              //read id of axi_m_5 AXI bus AR Channel
  output  [31:0]      araddr_axi_m_5;            //read address of axi_m_5 AXI bus AR Channel
  output  [7:0]       arlen_axi_m_5;             //read length of axi_m_5 AXI bus AR Channel
  output  [2:0]       arsize_axi_m_5;            //read size of axi_m_5 AXI bus AR Channel
  output  [1:0]       arburst_axi_m_5;           //read burst length of axi_m_5 AXI bus AR Channel
  output              arlock_axi_m_5;            //read lock of axi_m_5 AXI bus AR Channel
  output  [3:0]       arcache_axi_m_5;           //read cache field of axi_m_5 AXI bus AR Channel
  output  [2:0]       arprot_axi_m_5;            //read prot field of axi_m_5 AXI bus AR Channel
  output  [3:0]       arregion_axi_m_5;          //read region field of axi_m_5 AXI bus AR channel
  output              arvalid_axi_m_5;           //read valid of axi_m_5 AXI bus AR Channel
  output              arvalid_vect_axi_m_5;      //read valid vector of axi_m_5 AXI bus AR Channel
  input               arready_axi_m_5;           //read ready of axi_m_5 AXI bus AR Channel

  //R Channel
  input   [3:0]       rid_axi_m_5;               //read id of axi_m_5 AXI bus R Channel
  input   [31:0]      rdata_axi_m_5;             //read data of axi_m_5 AXI bus R Channel
  input   [1:0]       rresp_axi_m_5;             //read response status of axi_m_5 AXI bus R Channel
  input               rlast_axi_m_5;             //read last of axi_m_5 AXI bus R Channel
  input               rvalid_axi_m_5;            //read valid of axi_m_5 AXI bus R Channel
  output              rready_axi_m_5;            //read ready of axi_m_5 AXI bus R Channel

  //QV signals
  output  [3:0]       aw_qv_axi_m_5;             //Quality Value axi_m_5 AXI bus AW Channel
  output  [3:0]       ar_qv_axi_m_5;             //Quality value axi_m_5 AXI bus AR Channel

  ////master Interface Port axi_m_6


  //AW Channel
  output  [3:0]       awid_axi_m_6;              //write id of axi_m_6 AXI bus AW channel
  output  [31:0]      awaddr_axi_m_6;            //write address of axi_m_6 AXI bus AW channel
  output  [7:0]       awlen_axi_m_6;             //write length field of axi_m_6 AXI bus AW channel
  output  [2:0]       awsize_axi_m_6;            //write size of axi_m_6 AXI bus AW channel
  output  [1:0]       awburst_axi_m_6;           //write burst length of axi_m_6 AXI bus AW channel
  output              awlock_axi_m_6;            //write lock of axi_m_6 AXI bus AW channel
  output  [3:0]       awcache_axi_m_6;           //write cache field of axi_m_6 AXI bus AW channel
  output  [2:0]       awprot_axi_m_6;            //write prot field of axi_m_6 AXI bus AW channel
  output  [3:0]       awregion_axi_m_6;          //write region field of axi_m_6 AXI bus AW channel
  output              awvalid_axi_m_6;           //write valid of axi_m_6 AXI bus AW channel
  output              awvalid_vect_axi_m_6;      //write valid vector of axi_m_6 AXI bus AW Channel
  input               awready_axi_m_6;           //write ready of axi_m_6 AXI bus AW channel

  //W Channel
  output  [31:0]      wdata_axi_m_6;             //write data of axi_m_6 AXI bus W Channel
  output  [3:0]       wstrb_axi_m_6;             //write strobes of axi_m_6 AXI bus W Channel
  output              wlast_axi_m_6;             //write last of axi_m_6 AXI bus W Channel
  output              wvalid_axi_m_6;            //write valid of axi_m_6 AXI bus W Channel
  input               wready_axi_m_6;            //write ready of axi_m_6 AXI bus W Channel

  //B Channel
  input   [3:0]       bid_axi_m_6;               //b response id of axi_m_6 AXI bus B Channel
  input   [1:0]       bresp_axi_m_6;             //b response status of axi_m_6 AXI bus B Channel
  input               bvalid_axi_m_6;            //b response valid of axi_m_6 AXI bus B Channel
  output              bready_axi_m_6;            //b response ready of axi_m_6 AXI bus B Channel

  //AR Channel
  output  [3:0]       arid_axi_m_6;              //read id of axi_m_6 AXI bus AR Channel
  output  [31:0]      araddr_axi_m_6;            //read address of axi_m_6 AXI bus AR Channel
  output  [7:0]       arlen_axi_m_6;             //read length of axi_m_6 AXI bus AR Channel
  output  [2:0]       arsize_axi_m_6;            //read size of axi_m_6 AXI bus AR Channel
  output  [1:0]       arburst_axi_m_6;           //read burst length of axi_m_6 AXI bus AR Channel
  output              arlock_axi_m_6;            //read lock of axi_m_6 AXI bus AR Channel
  output  [3:0]       arcache_axi_m_6;           //read cache field of axi_m_6 AXI bus AR Channel
  output  [2:0]       arprot_axi_m_6;            //read prot field of axi_m_6 AXI bus AR Channel
  output  [3:0]       arregion_axi_m_6;          //read region field of axi_m_6 AXI bus AR channel
  output              arvalid_axi_m_6;           //read valid of axi_m_6 AXI bus AR Channel
  output              arvalid_vect_axi_m_6;      //read valid vector of axi_m_6 AXI bus AR Channel
  input               arready_axi_m_6;           //read ready of axi_m_6 AXI bus AR Channel

  //R Channel
  input   [3:0]       rid_axi_m_6;               //read id of axi_m_6 AXI bus R Channel
  input   [31:0]      rdata_axi_m_6;             //read data of axi_m_6 AXI bus R Channel
  input   [1:0]       rresp_axi_m_6;             //read response status of axi_m_6 AXI bus R Channel
  input               rlast_axi_m_6;             //read last of axi_m_6 AXI bus R Channel
  input               rvalid_axi_m_6;            //read valid of axi_m_6 AXI bus R Channel
  output              rready_axi_m_6;            //read ready of axi_m_6 AXI bus R Channel

  //QV signals
  output  [3:0]       aw_qv_axi_m_6;             //Quality Value axi_m_6 AXI bus AW Channel
  output  [3:0]       ar_qv_axi_m_6;             //Quality value axi_m_6 AXI bus AR Channel

  ////slave Interface Port axi_s_1


  //AW Channel
  input   [3:0]       awid_axi_s_1;              //write id of axi_s_1 AXI bus AW channel
  input   [31:0]      awaddr_axi_s_1;            //write address of axi_s_1 AXI bus AW channel
  input   [7:0]       awlen_axi_s_1;             //write length field of axi_s_1 AXI bus AW channel
  input   [2:0]       awsize_axi_s_1;            //write size of axi_s_1 AXI bus AW channel
  input   [1:0]       awburst_axi_s_1;           //write burst length of axi_s_1 AXI bus AW channel
  input               awlock_axi_s_1;            //write lock of axi_s_1 AXI bus AW channel
  input   [3:0]       awcache_axi_s_1;           //write cache field of axi_s_1 AXI bus AW channel
  input   [2:0]       awprot_axi_s_1;            //write prot field of axi_s_1 AXI bus AW channel
  input   [3:0]       awregion_axi_s_1;          //write region field of axi_s_1 AXI bus AW channel
  input               awvalid_axi_s_1;           //write valid of axi_s_1 AXI bus AW channel
  input   [3:0]       awvalid_vect_axi_s_1;      //write valid vector of axi_s_1 AXI bus AW Channel
  output              awready_axi_s_1;           //write ready of axi_s_1 AXI bus AW channel

  //W Channel
  input   [31:0]      wdata_axi_s_1;             //write data of axi_s_1 AXI bus W Channel
  input   [3:0]       wstrb_axi_s_1;             //write strobes of axi_s_1 AXI bus W Channel
  input               wlast_axi_s_1;             //write last of axi_s_1 AXI bus W Channel
  input               wvalid_axi_s_1;            //write valid of axi_s_1 AXI bus W Channel
  output              wready_axi_s_1;            //write ready of axi_s_1 AXI bus W Channel

  //B Channel
  output  [3:0]       bid_axi_s_1;               //b response id of axi_s_1 AXI bus B Channel
  output  [1:0]       bresp_axi_s_1;             //b response status of axi_s_1 AXI bus B Channel
  output              bvalid_axi_s_1;            //b response valid of axi_s_1 AXI bus B Channel
  input               bready_axi_s_1;            //b response ready of axi_s_1 AXI bus B Channel

  //AR Channel
  input   [3:0]       arid_axi_s_1;              //read id of axi_s_1 AXI bus AR Channel
  input   [31:0]      araddr_axi_s_1;            //read address of axi_s_1 AXI bus AR Channel
  input   [7:0]       arlen_axi_s_1;             //read length of axi_s_1 AXI bus AR Channel
  input   [2:0]       arsize_axi_s_1;            //read size of axi_s_1 AXI bus AR Channel
  input   [1:0]       arburst_axi_s_1;           //read burst length of axi_s_1 AXI bus AR Channel
  input               arlock_axi_s_1;            //read lock of axi_s_1 AXI bus AR Channel
  input   [3:0]       arcache_axi_s_1;           //read cache field of axi_s_1 AXI bus AR Channel
  input   [2:0]       arprot_axi_s_1;            //read prot field of axi_s_1 AXI bus AR Channel
  input   [3:0]       arregion_axi_s_1;          //read region field of axi_s_1 AXI bus AR channel
  input               arvalid_axi_s_1;           //read valid of axi_s_1 AXI bus AR Channel
  input   [3:0]       arvalid_vect_axi_s_1;      //read valid vector of axi_s_1 AXI bus AR Channel
  output              arready_axi_s_1;           //read ready of axi_s_1 AXI bus AR Channel

  //R Channel
  output  [3:0]       rid_axi_s_1;               //read id of axi_s_1 AXI bus R Channel
  output  [31:0]      rdata_axi_s_1;             //read data of axi_s_1 AXI bus R Channel
  output  [1:0]       rresp_axi_s_1;             //read response status of axi_s_1 AXI bus R Channel
  output              rlast_axi_s_1;             //read last of axi_s_1 AXI bus R Channel
  output              rvalid_axi_s_1;            //read valid of axi_s_1 AXI bus R Channel
  input               rready_axi_s_1;            //read ready of axi_s_1 AXI bus R Channel

  //QV signals
  input   [3:0]       aw_qv_axi_s_1;             //Quality Value axi_s_1 AXI bus AW Channel
  input   [3:0]       ar_qv_axi_s_1;             //Quality value axi_s_1 AXI bus AR Channel

  ////master Interface Port axi_m_7


  //AW Channel
  output  [3:0]       awid_axi_m_7;              //write id of axi_m_7 AXI bus AW channel
  output  [31:0]      awaddr_axi_m_7;            //write address of axi_m_7 AXI bus AW channel
  output  [7:0]       awlen_axi_m_7;             //write length field of axi_m_7 AXI bus AW channel
  output  [2:0]       awsize_axi_m_7;            //write size of axi_m_7 AXI bus AW channel
  output  [1:0]       awburst_axi_m_7;           //write burst length of axi_m_7 AXI bus AW channel
  output              awlock_axi_m_7;            //write lock of axi_m_7 AXI bus AW channel
  output  [3:0]       awcache_axi_m_7;           //write cache field of axi_m_7 AXI bus AW channel
  output  [2:0]       awprot_axi_m_7;            //write prot field of axi_m_7 AXI bus AW channel
  output  [3:0]       awregion_axi_m_7;          //write region field of axi_m_7 AXI bus AW channel
  output              awvalid_axi_m_7;           //write valid of axi_m_7 AXI bus AW channel
  output              awvalid_vect_axi_m_7;      //write valid vector of axi_m_7 AXI bus AW Channel
  input               awready_axi_m_7;           //write ready of axi_m_7 AXI bus AW channel

  //W Channel
  output  [31:0]      wdata_axi_m_7;             //write data of axi_m_7 AXI bus W Channel
  output  [3:0]       wstrb_axi_m_7;             //write strobes of axi_m_7 AXI bus W Channel
  output              wlast_axi_m_7;             //write last of axi_m_7 AXI bus W Channel
  output              wvalid_axi_m_7;            //write valid of axi_m_7 AXI bus W Channel
  input               wready_axi_m_7;            //write ready of axi_m_7 AXI bus W Channel

  //B Channel
  input   [3:0]       bid_axi_m_7;               //b response id of axi_m_7 AXI bus B Channel
  input   [1:0]       bresp_axi_m_7;             //b response status of axi_m_7 AXI bus B Channel
  input               bvalid_axi_m_7;            //b response valid of axi_m_7 AXI bus B Channel
  output              bready_axi_m_7;            //b response ready of axi_m_7 AXI bus B Channel

  //AR Channel
  output  [3:0]       arid_axi_m_7;              //read id of axi_m_7 AXI bus AR Channel
  output  [31:0]      araddr_axi_m_7;            //read address of axi_m_7 AXI bus AR Channel
  output  [7:0]       arlen_axi_m_7;             //read length of axi_m_7 AXI bus AR Channel
  output  [2:0]       arsize_axi_m_7;            //read size of axi_m_7 AXI bus AR Channel
  output  [1:0]       arburst_axi_m_7;           //read burst length of axi_m_7 AXI bus AR Channel
  output              arlock_axi_m_7;            //read lock of axi_m_7 AXI bus AR Channel
  output  [3:0]       arcache_axi_m_7;           //read cache field of axi_m_7 AXI bus AR Channel
  output  [2:0]       arprot_axi_m_7;            //read prot field of axi_m_7 AXI bus AR Channel
  output  [3:0]       arregion_axi_m_7;          //read region field of axi_m_7 AXI bus AR channel
  output              arvalid_axi_m_7;           //read valid of axi_m_7 AXI bus AR Channel
  output              arvalid_vect_axi_m_7;      //read valid vector of axi_m_7 AXI bus AR Channel
  input               arready_axi_m_7;           //read ready of axi_m_7 AXI bus AR Channel

  //R Channel
  input   [3:0]       rid_axi_m_7;               //read id of axi_m_7 AXI bus R Channel
  input   [31:0]      rdata_axi_m_7;             //read data of axi_m_7 AXI bus R Channel
  input   [1:0]       rresp_axi_m_7;             //read response status of axi_m_7 AXI bus R Channel
  input               rlast_axi_m_7;             //read last of axi_m_7 AXI bus R Channel
  input               rvalid_axi_m_7;            //read valid of axi_m_7 AXI bus R Channel
  output              rready_axi_m_7;            //read ready of axi_m_7 AXI bus R Channel

  //QV signals
  output  [3:0]       aw_qv_axi_m_7;             //Quality Value axi_m_7 AXI bus AW Channel
  output  [3:0]       ar_qv_axi_m_7;             //Quality value axi_m_7 AXI bus AR Channel

  ////master Interface Port axi_m_8


  //AW Channel
  output  [3:0]       awid_axi_m_8;              //write id of axi_m_8 AXI bus AW channel
  output  [31:0]      awaddr_axi_m_8;            //write address of axi_m_8 AXI bus AW channel
  output  [7:0]       awlen_axi_m_8;             //write length field of axi_m_8 AXI bus AW channel
  output  [2:0]       awsize_axi_m_8;            //write size of axi_m_8 AXI bus AW channel
  output  [1:0]       awburst_axi_m_8;           //write burst length of axi_m_8 AXI bus AW channel
  output              awlock_axi_m_8;            //write lock of axi_m_8 AXI bus AW channel
  output  [3:0]       awcache_axi_m_8;           //write cache field of axi_m_8 AXI bus AW channel
  output  [2:0]       awprot_axi_m_8;            //write prot field of axi_m_8 AXI bus AW channel
  output  [3:0]       awregion_axi_m_8;          //write region field of axi_m_8 AXI bus AW channel
  output              awvalid_axi_m_8;           //write valid of axi_m_8 AXI bus AW channel
  output              awvalid_vect_axi_m_8;      //write valid vector of axi_m_8 AXI bus AW Channel
  input               awready_axi_m_8;           //write ready of axi_m_8 AXI bus AW channel

  //W Channel
  output  [31:0]      wdata_axi_m_8;             //write data of axi_m_8 AXI bus W Channel
  output  [3:0]       wstrb_axi_m_8;             //write strobes of axi_m_8 AXI bus W Channel
  output              wlast_axi_m_8;             //write last of axi_m_8 AXI bus W Channel
  output              wvalid_axi_m_8;            //write valid of axi_m_8 AXI bus W Channel
  input               wready_axi_m_8;            //write ready of axi_m_8 AXI bus W Channel

  //B Channel
  input   [3:0]       bid_axi_m_8;               //b response id of axi_m_8 AXI bus B Channel
  input   [1:0]       bresp_axi_m_8;             //b response status of axi_m_8 AXI bus B Channel
  input               bvalid_axi_m_8;            //b response valid of axi_m_8 AXI bus B Channel
  output              bready_axi_m_8;            //b response ready of axi_m_8 AXI bus B Channel

  //AR Channel
  output  [3:0]       arid_axi_m_8;              //read id of axi_m_8 AXI bus AR Channel
  output  [31:0]      araddr_axi_m_8;            //read address of axi_m_8 AXI bus AR Channel
  output  [7:0]       arlen_axi_m_8;             //read length of axi_m_8 AXI bus AR Channel
  output  [2:0]       arsize_axi_m_8;            //read size of axi_m_8 AXI bus AR Channel
  output  [1:0]       arburst_axi_m_8;           //read burst length of axi_m_8 AXI bus AR Channel
  output              arlock_axi_m_8;            //read lock of axi_m_8 AXI bus AR Channel
  output  [3:0]       arcache_axi_m_8;           //read cache field of axi_m_8 AXI bus AR Channel
  output  [2:0]       arprot_axi_m_8;            //read prot field of axi_m_8 AXI bus AR Channel
  output  [3:0]       arregion_axi_m_8;          //read region field of axi_m_8 AXI bus AR channel
  output              arvalid_axi_m_8;           //read valid of axi_m_8 AXI bus AR Channel
  output              arvalid_vect_axi_m_8;      //read valid vector of axi_m_8 AXI bus AR Channel
  input               arready_axi_m_8;           //read ready of axi_m_8 AXI bus AR Channel

  //R Channel
  input   [3:0]       rid_axi_m_8;               //read id of axi_m_8 AXI bus R Channel
  input   [31:0]      rdata_axi_m_8;             //read data of axi_m_8 AXI bus R Channel
  input   [1:0]       rresp_axi_m_8;             //read response status of axi_m_8 AXI bus R Channel
  input               rlast_axi_m_8;             //read last of axi_m_8 AXI bus R Channel
  input               rvalid_axi_m_8;            //read valid of axi_m_8 AXI bus R Channel
  output              rready_axi_m_8;            //read ready of axi_m_8 AXI bus R Channel

  //QV signals
  output  [3:0]       aw_qv_axi_m_8;             //Quality Value axi_m_8 AXI bus AW Channel
  output  [3:0]       ar_qv_axi_m_8;             //Quality value axi_m_8 AXI bus AR Channel

  ////master Interface Port axi_m_9


  //AW Channel
  output  [3:0]       awid_axi_m_9;              //write id of axi_m_9 AXI bus AW channel
  output  [31:0]      awaddr_axi_m_9;            //write address of axi_m_9 AXI bus AW channel
  output  [7:0]       awlen_axi_m_9;             //write length field of axi_m_9 AXI bus AW channel
  output  [2:0]       awsize_axi_m_9;            //write size of axi_m_9 AXI bus AW channel
  output  [1:0]       awburst_axi_m_9;           //write burst length of axi_m_9 AXI bus AW channel
  output              awlock_axi_m_9;            //write lock of axi_m_9 AXI bus AW channel
  output  [3:0]       awcache_axi_m_9;           //write cache field of axi_m_9 AXI bus AW channel
  output  [2:0]       awprot_axi_m_9;            //write prot field of axi_m_9 AXI bus AW channel
  output  [3:0]       awregion_axi_m_9;          //write region field of axi_m_9 AXI bus AW channel
  output              awvalid_axi_m_9;           //write valid of axi_m_9 AXI bus AW channel
  output              awvalid_vect_axi_m_9;      //write valid vector of axi_m_9 AXI bus AW Channel
  input               awready_axi_m_9;           //write ready of axi_m_9 AXI bus AW channel

  //W Channel
  output  [31:0]      wdata_axi_m_9;             //write data of axi_m_9 AXI bus W Channel
  output  [3:0]       wstrb_axi_m_9;             //write strobes of axi_m_9 AXI bus W Channel
  output              wlast_axi_m_9;             //write last of axi_m_9 AXI bus W Channel
  output              wvalid_axi_m_9;            //write valid of axi_m_9 AXI bus W Channel
  input               wready_axi_m_9;            //write ready of axi_m_9 AXI bus W Channel

  //B Channel
  input   [3:0]       bid_axi_m_9;               //b response id of axi_m_9 AXI bus B Channel
  input   [1:0]       bresp_axi_m_9;             //b response status of axi_m_9 AXI bus B Channel
  input               bvalid_axi_m_9;            //b response valid of axi_m_9 AXI bus B Channel
  output              bready_axi_m_9;            //b response ready of axi_m_9 AXI bus B Channel

  //AR Channel
  output  [3:0]       arid_axi_m_9;              //read id of axi_m_9 AXI bus AR Channel
  output  [31:0]      araddr_axi_m_9;            //read address of axi_m_9 AXI bus AR Channel
  output  [7:0]       arlen_axi_m_9;             //read length of axi_m_9 AXI bus AR Channel
  output  [2:0]       arsize_axi_m_9;            //read size of axi_m_9 AXI bus AR Channel
  output  [1:0]       arburst_axi_m_9;           //read burst length of axi_m_9 AXI bus AR Channel
  output              arlock_axi_m_9;            //read lock of axi_m_9 AXI bus AR Channel
  output  [3:0]       arcache_axi_m_9;           //read cache field of axi_m_9 AXI bus AR Channel
  output  [2:0]       arprot_axi_m_9;            //read prot field of axi_m_9 AXI bus AR Channel
  output  [3:0]       arregion_axi_m_9;          //read region field of axi_m_9 AXI bus AR channel
  output              arvalid_axi_m_9;           //read valid of axi_m_9 AXI bus AR Channel
  output              arvalid_vect_axi_m_9;      //read valid vector of axi_m_9 AXI bus AR Channel
  input               arready_axi_m_9;           //read ready of axi_m_9 AXI bus AR Channel

  //R Channel
  input   [3:0]       rid_axi_m_9;               //read id of axi_m_9 AXI bus R Channel
  input   [31:0]      rdata_axi_m_9;             //read data of axi_m_9 AXI bus R Channel
  input   [1:0]       rresp_axi_m_9;             //read response status of axi_m_9 AXI bus R Channel
  input               rlast_axi_m_9;             //read last of axi_m_9 AXI bus R Channel
  input               rvalid_axi_m_9;            //read valid of axi_m_9 AXI bus R Channel
  output              rready_axi_m_9;            //read ready of axi_m_9 AXI bus R Channel

  //QV signals
  output  [3:0]       aw_qv_axi_m_9;             //Quality Value axi_m_9 AXI bus AW Channel
  output  [3:0]       ar_qv_axi_m_9;             //Quality value axi_m_9 AXI bus AR Channel

  ////master Interface Port axi_m_4


  //AW Channel
  output  [3:0]       awid_axi_m_4;              //write id of axi_m_4 AXI bus AW channel
  output  [31:0]      awaddr_axi_m_4;            //write address of axi_m_4 AXI bus AW channel
  output  [7:0]       awlen_axi_m_4;             //write length field of axi_m_4 AXI bus AW channel
  output  [2:0]       awsize_axi_m_4;            //write size of axi_m_4 AXI bus AW channel
  output  [1:0]       awburst_axi_m_4;           //write burst length of axi_m_4 AXI bus AW channel
  output              awlock_axi_m_4;            //write lock of axi_m_4 AXI bus AW channel
  output  [3:0]       awcache_axi_m_4;           //write cache field of axi_m_4 AXI bus AW channel
  output  [2:0]       awprot_axi_m_4;            //write prot field of axi_m_4 AXI bus AW channel
  output  [3:0]       awregion_axi_m_4;          //write region field of axi_m_4 AXI bus AW channel
  output              awvalid_axi_m_4;           //write valid of axi_m_4 AXI bus AW channel
  output              awvalid_vect_axi_m_4;      //write valid vector of axi_m_4 AXI bus AW Channel
  input               awready_axi_m_4;           //write ready of axi_m_4 AXI bus AW channel

  //W Channel
  output  [31:0]      wdata_axi_m_4;             //write data of axi_m_4 AXI bus W Channel
  output  [3:0]       wstrb_axi_m_4;             //write strobes of axi_m_4 AXI bus W Channel
  output              wlast_axi_m_4;             //write last of axi_m_4 AXI bus W Channel
  output              wvalid_axi_m_4;            //write valid of axi_m_4 AXI bus W Channel
  input               wready_axi_m_4;            //write ready of axi_m_4 AXI bus W Channel

  //B Channel
  input   [3:0]       bid_axi_m_4;               //b response id of axi_m_4 AXI bus B Channel
  input   [1:0]       bresp_axi_m_4;             //b response status of axi_m_4 AXI bus B Channel
  input               bvalid_axi_m_4;            //b response valid of axi_m_4 AXI bus B Channel
  output              bready_axi_m_4;            //b response ready of axi_m_4 AXI bus B Channel

  //AR Channel
  output  [3:0]       arid_axi_m_4;              //read id of axi_m_4 AXI bus AR Channel
  output  [31:0]      araddr_axi_m_4;            //read address of axi_m_4 AXI bus AR Channel
  output  [7:0]       arlen_axi_m_4;             //read length of axi_m_4 AXI bus AR Channel
  output  [2:0]       arsize_axi_m_4;            //read size of axi_m_4 AXI bus AR Channel
  output  [1:0]       arburst_axi_m_4;           //read burst length of axi_m_4 AXI bus AR Channel
  output              arlock_axi_m_4;            //read lock of axi_m_4 AXI bus AR Channel
  output  [3:0]       arcache_axi_m_4;           //read cache field of axi_m_4 AXI bus AR Channel
  output  [2:0]       arprot_axi_m_4;            //read prot field of axi_m_4 AXI bus AR Channel
  output  [3:0]       arregion_axi_m_4;          //read region field of axi_m_4 AXI bus AR channel
  output              arvalid_axi_m_4;           //read valid of axi_m_4 AXI bus AR Channel
  output              arvalid_vect_axi_m_4;      //read valid vector of axi_m_4 AXI bus AR Channel
  input               arready_axi_m_4;           //read ready of axi_m_4 AXI bus AR Channel

  //R Channel
  input   [3:0]       rid_axi_m_4;               //read id of axi_m_4 AXI bus R Channel
  input   [31:0]      rdata_axi_m_4;             //read data of axi_m_4 AXI bus R Channel
  input   [1:0]       rresp_axi_m_4;             //read response status of axi_m_4 AXI bus R Channel
  input               rlast_axi_m_4;             //read last of axi_m_4 AXI bus R Channel
  input               rvalid_axi_m_4;            //read valid of axi_m_4 AXI bus R Channel
  output              rready_axi_m_4;            //read ready of axi_m_4 AXI bus R Channel

  //QV signals
  output  [3:0]       aw_qv_axi_m_4;             //Quality Value axi_m_4 AXI bus AW Channel
  output  [3:0]       ar_qv_axi_m_4;             //Quality value axi_m_4 AXI bus AR Channel

  //Clock and reset signals
  input               aclk;                      //main clock
  input               aresetn;                   //main reset


  //------------------------------------------------------------------------------
  // Wires 
  //------------------------------------------------------------------------------


    // Merging of region and user signals
    wire  [3:0]                 awuseri_axi_s_0;
    wire  [3:0]                 aruseri_axi_s_0;
    wire  [3:0]                 awuseri_axi_s_1;
    wire  [3:0]                 aruseri_axi_s_1;
    wire  [3:0]                 awuseri_axi_m_0;
    wire  [3:0]                 aruseri_axi_m_0;
    wire  [3:0]                 awuseri_axi_m_1;
    wire  [3:0]                 aruseri_axi_m_1;
    wire  [3:0]                 awuseri_axi_m_5;
    wire  [3:0]                 aruseri_axi_m_5;
    wire  [3:0]                 awuseri_axi_m_6;
    wire  [3:0]                 aruseri_axi_m_6;
    wire  [3:0]                 awuseri_axi_m_7;
    wire  [3:0]                 aruseri_axi_m_7;
    wire  [3:0]                 awuseri_axi_m_8;
    wire  [3:0]                 aruseri_axi_m_8;
    wire  [3:0]                 awuseri_axi_m_9;
    wire  [3:0]                 aruseri_axi_m_9;
    wire  [3:0]                 awuseri_axi_m_4;
    wire  [3:0]                 aruseri_axi_m_4;
    wire  [3:0]                 awuseri_axi_m_2;
    wire  [3:0]                 aruseri_axi_m_2;
    // Connects SlaveInterface 0 to MasterInterface 0
    // Write Address Channel
    wire  [3:0]                 awuser_0_0;
    wire  [3:0]                 awid_0_0;
    wire  [31:0]                awaddr_0_0;
    wire  [7:0]                 awlen_0_0;
    wire  [2:0]                 awsize_0_0;
    wire  [1:0]                 awburst_0_0;
    wire                        awlock_0_0;
    wire  [3:0]                 awcache_0_0;
    wire  [2:0]                 awprot_0_0;
    wire                        awvalid_0_0;
    wire                   awvalid_vect_0_0;
    wire                        awready_0_0;
    wire  [3:0]                 aw_qv_0_0;
   
    // Write Channel
    wire  [31:0]                wdata_0_0;
    wire  [3:0]                 wstrb_0_0;
    wire                        wlast_0_0;
    wire                        wvalid_0_0;
    wire                        wready_0_0;

    // Write Response Channel
    wire  [3:0]                 bid_0_0;
    wire  [1:0]                 bresp_0_0;
    wire                        bvalid_0_0;
    wire                        bready_0_0;

    // Read Address Channel
    wire  [3:0]                 aruser_0_0;
    wire  [3:0]                 arid_0_0;
    wire  [31:0]                araddr_0_0;
    wire  [7:0]                 arlen_0_0;
    wire  [2:0]                 arsize_0_0;
    wire  [1:0]                 arburst_0_0;
    wire                        arlock_0_0;
    wire  [3:0]                 arcache_0_0;
    wire  [2:0]                 arprot_0_0;
    wire                        arvalid_0_0;
    wire                   arvalid_vect_0_0;
    wire                        arready_0_0;
    wire  [3:0]                 ar_qv_0_0;
   
    // Read Channel
    wire  [3:0]                 rid_0_0;
    wire  [31:0]                rdata_0_0;
    wire  [1:0]                 rresp_0_0;
    wire                        rlast_0_0;
    wire                        rvalid_0_0;
    wire                        rready_0_0;


    // Connects SlaveInterface 0 to MasterInterface 1
    // Write Address Channel
    wire  [3:0]                 awuser_0_1;
    wire  [3:0]                 awid_0_1;
    wire  [31:0]                awaddr_0_1;
    wire  [7:0]                 awlen_0_1;
    wire  [2:0]                 awsize_0_1;
    wire  [1:0]                 awburst_0_1;
    wire                        awlock_0_1;
    wire  [3:0]                 awcache_0_1;
    wire  [2:0]                 awprot_0_1;
    wire                        awvalid_0_1;
    wire                   awvalid_vect_0_1;
    wire                        awready_0_1;
    wire  [3:0]                 aw_qv_0_1;
   
    // Write Channel
    wire  [31:0]                wdata_0_1;
    wire  [3:0]                 wstrb_0_1;
    wire                        wlast_0_1;
    wire                        wvalid_0_1;
    wire                        wready_0_1;

    // Write Response Channel
    wire  [3:0]                 bid_0_1;
    wire  [1:0]                 bresp_0_1;
    wire                        bvalid_0_1;
    wire                        bready_0_1;

    // Read Address Channel
    wire  [3:0]                 aruser_0_1;
    wire  [3:0]                 arid_0_1;
    wire  [31:0]                araddr_0_1;
    wire  [7:0]                 arlen_0_1;
    wire  [2:0]                 arsize_0_1;
    wire  [1:0]                 arburst_0_1;
    wire                        arlock_0_1;
    wire  [3:0]                 arcache_0_1;
    wire  [2:0]                 arprot_0_1;
    wire                        arvalid_0_1;
    wire                   arvalid_vect_0_1;
    wire                        arready_0_1;
    wire  [3:0]                 ar_qv_0_1;
   
    // Read Channel
    wire  [3:0]                 rid_0_1;
    wire  [31:0]                rdata_0_1;
    wire  [1:0]                 rresp_0_1;
    wire                        rlast_0_1;
    wire                        rvalid_0_1;
    wire                        rready_0_1;


    // Connects SlaveInterface 0 to MasterInterface 2
    // Write Address Channel
    wire  [3:0]                 awuser_0_2;
    wire  [3:0]                 awid_0_2;
    wire  [31:0]                awaddr_0_2;
    wire  [7:0]                 awlen_0_2;
    wire  [2:0]                 awsize_0_2;
    wire  [1:0]                 awburst_0_2;
    wire                        awlock_0_2;
    wire  [3:0]                 awcache_0_2;
    wire  [2:0]                 awprot_0_2;
    wire                        awvalid_0_2;
    wire                   awvalid_vect_0_2;
    wire                        awready_0_2;
    wire  [3:0]                 aw_qv_0_2;
   
    // Write Channel
    wire  [31:0]                wdata_0_2;
    wire  [3:0]                 wstrb_0_2;
    wire                        wlast_0_2;
    wire                        wvalid_0_2;
    wire                        wready_0_2;

    // Write Response Channel
    wire  [3:0]                 bid_0_2;
    wire  [1:0]                 bresp_0_2;
    wire                        bvalid_0_2;
    wire                        bready_0_2;

    // Read Address Channel
    wire  [3:0]                 aruser_0_2;
    wire  [3:0]                 arid_0_2;
    wire  [31:0]                araddr_0_2;
    wire  [7:0]                 arlen_0_2;
    wire  [2:0]                 arsize_0_2;
    wire  [1:0]                 arburst_0_2;
    wire                        arlock_0_2;
    wire  [3:0]                 arcache_0_2;
    wire  [2:0]                 arprot_0_2;
    wire                        arvalid_0_2;
    wire                   arvalid_vect_0_2;
    wire                        arready_0_2;
    wire  [3:0]                 ar_qv_0_2;
   
    // Read Channel
    wire  [3:0]                 rid_0_2;
    wire  [31:0]                rdata_0_2;
    wire  [1:0]                 rresp_0_2;
    wire                        rlast_0_2;
    wire                        rvalid_0_2;
    wire                        rready_0_2;


    // Connects SlaveInterface 0 to MasterInterface 3
    // Write Address Channel
    wire  [3:0]                 awuser_0_3;
    wire  [3:0]                 awid_0_3;
    wire  [31:0]                awaddr_0_3;
    wire  [7:0]                 awlen_0_3;
    wire  [2:0]                 awsize_0_3;
    wire  [1:0]                 awburst_0_3;
    wire                        awlock_0_3;
    wire  [3:0]                 awcache_0_3;
    wire  [2:0]                 awprot_0_3;
    wire                        awvalid_0_3;
    wire                   awvalid_vect_0_3;
    wire                        awready_0_3;
    wire  [3:0]                 aw_qv_0_3;
   
    // Write Channel
    wire  [31:0]                wdata_0_3;
    wire  [3:0]                 wstrb_0_3;
    wire                        wlast_0_3;
    wire                        wvalid_0_3;
    wire                        wready_0_3;

    // Write Response Channel
    wire  [3:0]                 bid_0_3;
    wire  [1:0]                 bresp_0_3;
    wire                        bvalid_0_3;
    wire                        bready_0_3;

    // Read Address Channel
    wire  [3:0]                 aruser_0_3;
    wire  [3:0]                 arid_0_3;
    wire  [31:0]                araddr_0_3;
    wire  [7:0]                 arlen_0_3;
    wire  [2:0]                 arsize_0_3;
    wire  [1:0]                 arburst_0_3;
    wire                        arlock_0_3;
    wire  [3:0]                 arcache_0_3;
    wire  [2:0]                 arprot_0_3;
    wire                        arvalid_0_3;
    wire                   arvalid_vect_0_3;
    wire                        arready_0_3;
    wire  [3:0]                 ar_qv_0_3;
   
    // Read Channel
    wire  [3:0]                 rid_0_3;
    wire  [31:0]                rdata_0_3;
    wire  [1:0]                 rresp_0_3;
    wire                        rlast_0_3;
    wire                        rvalid_0_3;
    wire                        rready_0_3;


    // Connects SlaveInterface 0 to MasterInterface 4
    // Write Address Channel
    wire  [3:0]                 awuser_0_4;
    wire  [3:0]                 awid_0_4;
    wire  [31:0]                awaddr_0_4;
    wire  [7:0]                 awlen_0_4;
    wire  [2:0]                 awsize_0_4;
    wire  [1:0]                 awburst_0_4;
    wire                        awlock_0_4;
    wire  [3:0]                 awcache_0_4;
    wire  [2:0]                 awprot_0_4;
    wire                        awvalid_0_4;
    wire                   awvalid_vect_0_4;
    wire                        awready_0_4;
    wire  [3:0]                 aw_qv_0_4;
   
    // Write Channel
    wire  [31:0]                wdata_0_4;
    wire  [3:0]                 wstrb_0_4;
    wire                        wlast_0_4;
    wire                        wvalid_0_4;
    wire                        wready_0_4;

    // Write Response Channel
    wire  [3:0]                 bid_0_4;
    wire  [1:0]                 bresp_0_4;
    wire                        bvalid_0_4;
    wire                        bready_0_4;

    // Read Address Channel
    wire  [3:0]                 aruser_0_4;
    wire  [3:0]                 arid_0_4;
    wire  [31:0]                araddr_0_4;
    wire  [7:0]                 arlen_0_4;
    wire  [2:0]                 arsize_0_4;
    wire  [1:0]                 arburst_0_4;
    wire                        arlock_0_4;
    wire  [3:0]                 arcache_0_4;
    wire  [2:0]                 arprot_0_4;
    wire                        arvalid_0_4;
    wire                   arvalid_vect_0_4;
    wire                        arready_0_4;
    wire  [3:0]                 ar_qv_0_4;
   
    // Read Channel
    wire  [3:0]                 rid_0_4;
    wire  [31:0]                rdata_0_4;
    wire  [1:0]                 rresp_0_4;
    wire                        rlast_0_4;
    wire                        rvalid_0_4;
    wire                        rready_0_4;


    // Connects SlaveInterface 0 to MasterInterface 5
    // Write Address Channel
    wire  [3:0]                 awuser_0_5;
    wire  [3:0]                 awid_0_5;
    wire  [31:0]                awaddr_0_5;
    wire  [7:0]                 awlen_0_5;
    wire  [2:0]                 awsize_0_5;
    wire  [1:0]                 awburst_0_5;
    wire                        awlock_0_5;
    wire  [3:0]                 awcache_0_5;
    wire  [2:0]                 awprot_0_5;
    wire                        awvalid_0_5;
    wire                   awvalid_vect_0_5;
    wire                        awready_0_5;
    wire  [3:0]                 aw_qv_0_5;
   
    // Write Channel
    wire  [31:0]                wdata_0_5;
    wire  [3:0]                 wstrb_0_5;
    wire                        wlast_0_5;
    wire                        wvalid_0_5;
    wire                        wready_0_5;

    // Write Response Channel
    wire  [3:0]                 bid_0_5;
    wire  [1:0]                 bresp_0_5;
    wire                        bvalid_0_5;
    wire                        bready_0_5;

    // Read Address Channel
    wire  [3:0]                 aruser_0_5;
    wire  [3:0]                 arid_0_5;
    wire  [31:0]                araddr_0_5;
    wire  [7:0]                 arlen_0_5;
    wire  [2:0]                 arsize_0_5;
    wire  [1:0]                 arburst_0_5;
    wire                        arlock_0_5;
    wire  [3:0]                 arcache_0_5;
    wire  [2:0]                 arprot_0_5;
    wire                        arvalid_0_5;
    wire                   arvalid_vect_0_5;
    wire                        arready_0_5;
    wire  [3:0]                 ar_qv_0_5;
   
    // Read Channel
    wire  [3:0]                 rid_0_5;
    wire  [31:0]                rdata_0_5;
    wire  [1:0]                 rresp_0_5;
    wire                        rlast_0_5;
    wire                        rvalid_0_5;
    wire                        rready_0_5;


    // Connects SlaveInterface 0 to MasterInterface 6
    // Write Address Channel
    wire  [3:0]                 awuser_0_6;
    wire  [3:0]                 awid_0_6;
    wire  [31:0]                awaddr_0_6;
    wire  [7:0]                 awlen_0_6;
    wire  [2:0]                 awsize_0_6;
    wire  [1:0]                 awburst_0_6;
    wire                        awlock_0_6;
    wire  [3:0]                 awcache_0_6;
    wire  [2:0]                 awprot_0_6;
    wire                        awvalid_0_6;
    wire                   awvalid_vect_0_6;
    wire                        awready_0_6;
    wire  [3:0]                 aw_qv_0_6;
   
    // Write Channel
    wire  [31:0]                wdata_0_6;
    wire  [3:0]                 wstrb_0_6;
    wire                        wlast_0_6;
    wire                        wvalid_0_6;
    wire                        wready_0_6;

    // Write Response Channel
    wire  [3:0]                 bid_0_6;
    wire  [1:0]                 bresp_0_6;
    wire                        bvalid_0_6;
    wire                        bready_0_6;

    // Read Address Channel
    wire  [3:0]                 aruser_0_6;
    wire  [3:0]                 arid_0_6;
    wire  [31:0]                araddr_0_6;
    wire  [7:0]                 arlen_0_6;
    wire  [2:0]                 arsize_0_6;
    wire  [1:0]                 arburst_0_6;
    wire                        arlock_0_6;
    wire  [3:0]                 arcache_0_6;
    wire  [2:0]                 arprot_0_6;
    wire                        arvalid_0_6;
    wire                   arvalid_vect_0_6;
    wire                        arready_0_6;
    wire  [3:0]                 ar_qv_0_6;
   
    // Read Channel
    wire  [3:0]                 rid_0_6;
    wire  [31:0]                rdata_0_6;
    wire  [1:0]                 rresp_0_6;
    wire                        rlast_0_6;
    wire                        rvalid_0_6;
    wire                        rready_0_6;


    // Connects SlaveInterface 0 to MasterInterface 7
    // Write Address Channel
    wire  [3:0]                 awuser_0_7;
    wire  [3:0]                 awid_0_7;
    wire  [31:0]                awaddr_0_7;
    wire  [7:0]                 awlen_0_7;
    wire  [2:0]                 awsize_0_7;
    wire  [1:0]                 awburst_0_7;
    wire                        awlock_0_7;
    wire  [3:0]                 awcache_0_7;
    wire  [2:0]                 awprot_0_7;
    wire                        awvalid_0_7;
    wire                   awvalid_vect_0_7;
    wire                        awready_0_7;
    wire  [3:0]                 aw_qv_0_7;
   
    // Write Channel
    wire  [31:0]                wdata_0_7;
    wire  [3:0]                 wstrb_0_7;
    wire                        wlast_0_7;
    wire                        wvalid_0_7;
    wire                        wready_0_7;

    // Write Response Channel
    wire  [3:0]                 bid_0_7;
    wire  [1:0]                 bresp_0_7;
    wire                        bvalid_0_7;
    wire                        bready_0_7;

    // Read Address Channel
    wire  [3:0]                 aruser_0_7;
    wire  [3:0]                 arid_0_7;
    wire  [31:0]                araddr_0_7;
    wire  [7:0]                 arlen_0_7;
    wire  [2:0]                 arsize_0_7;
    wire  [1:0]                 arburst_0_7;
    wire                        arlock_0_7;
    wire  [3:0]                 arcache_0_7;
    wire  [2:0]                 arprot_0_7;
    wire                        arvalid_0_7;
    wire                   arvalid_vect_0_7;
    wire                        arready_0_7;
    wire  [3:0]                 ar_qv_0_7;
   
    // Read Channel
    wire  [3:0]                 rid_0_7;
    wire  [31:0]                rdata_0_7;
    wire  [1:0]                 rresp_0_7;
    wire                        rlast_0_7;
    wire                        rvalid_0_7;
    wire                        rready_0_7;


    // Connects SlaveInterface 0 to MasterInterface 8
    // Write Address Channel
    wire  [3:0]                 awuser_0_8;
    wire  [3:0]                 awid_0_8;
    wire  [31:0]                awaddr_0_8;
    wire  [7:0]                 awlen_0_8;
    wire  [2:0]                 awsize_0_8;
    wire  [1:0]                 awburst_0_8;
    wire                        awlock_0_8;
    wire  [3:0]                 awcache_0_8;
    wire  [2:0]                 awprot_0_8;
    wire                        awvalid_0_8;
    wire                   awvalid_vect_0_8;
    wire                        awready_0_8;
    wire  [3:0]                 aw_qv_0_8;
   
    // Write Channel
    wire  [31:0]                wdata_0_8;
    wire  [3:0]                 wstrb_0_8;
    wire                        wlast_0_8;
    wire                        wvalid_0_8;
    wire                        wready_0_8;

    // Write Response Channel
    wire  [3:0]                 bid_0_8;
    wire  [1:0]                 bresp_0_8;
    wire                        bvalid_0_8;
    wire                        bready_0_8;

    // Read Address Channel
    wire  [3:0]                 aruser_0_8;
    wire  [3:0]                 arid_0_8;
    wire  [31:0]                araddr_0_8;
    wire  [7:0]                 arlen_0_8;
    wire  [2:0]                 arsize_0_8;
    wire  [1:0]                 arburst_0_8;
    wire                        arlock_0_8;
    wire  [3:0]                 arcache_0_8;
    wire  [2:0]                 arprot_0_8;
    wire                        arvalid_0_8;
    wire                   arvalid_vect_0_8;
    wire                        arready_0_8;
    wire  [3:0]                 ar_qv_0_8;
   
    // Read Channel
    wire  [3:0]                 rid_0_8;
    wire  [31:0]                rdata_0_8;
    wire  [1:0]                 rresp_0_8;
    wire                        rlast_0_8;
    wire                        rvalid_0_8;
    wire                        rready_0_8;


    // Connects SlaveInterface 1 to MasterInterface 2
    // Write Address Channel
    wire  [3:0]                 awuser_1_2;
    wire  [3:0]                 awid_1_2;
    wire  [31:0]                awaddr_1_2;
    wire  [7:0]                 awlen_1_2;
    wire  [2:0]                 awsize_1_2;
    wire  [1:0]                 awburst_1_2;
    wire                        awlock_1_2;
    wire  [3:0]                 awcache_1_2;
    wire  [2:0]                 awprot_1_2;
    wire                        awvalid_1_2;
    wire                   awvalid_vect_1_2;
    wire                        awready_1_2;
    wire  [3:0]                 aw_qv_1_2;
   
    // Write Channel
    wire  [31:0]                wdata_1_2;
    wire  [3:0]                 wstrb_1_2;
    wire                        wlast_1_2;
    wire                        wvalid_1_2;
    wire                        wready_1_2;

    // Write Response Channel
    wire  [3:0]                 bid_1_2;
    wire  [1:0]                 bresp_1_2;
    wire                        bvalid_1_2;
    wire                        bready_1_2;

    // Read Address Channel
    wire  [3:0]                 aruser_1_2;
    wire  [3:0]                 arid_1_2;
    wire  [31:0]                araddr_1_2;
    wire  [7:0]                 arlen_1_2;
    wire  [2:0]                 arsize_1_2;
    wire  [1:0]                 arburst_1_2;
    wire                        arlock_1_2;
    wire  [3:0]                 arcache_1_2;
    wire  [2:0]                 arprot_1_2;
    wire                        arvalid_1_2;
    wire                   arvalid_vect_1_2;
    wire                        arready_1_2;
    wire  [3:0]                 ar_qv_1_2;
   
    // Read Channel
    wire  [3:0]                 rid_1_2;
    wire  [31:0]                rdata_1_2;
    wire  [1:0]                 rresp_1_2;
    wire                        rlast_1_2;
    wire                        rvalid_1_2;
    wire                        rready_1_2;


    // Connects SlaveInterface 1 to MasterInterface 3
    // Write Address Channel
    wire  [3:0]                 awuser_1_3;
    wire  [3:0]                 awid_1_3;
    wire  [31:0]                awaddr_1_3;
    wire  [7:0]                 awlen_1_3;
    wire  [2:0]                 awsize_1_3;
    wire  [1:0]                 awburst_1_3;
    wire                        awlock_1_3;
    wire  [3:0]                 awcache_1_3;
    wire  [2:0]                 awprot_1_3;
    wire                        awvalid_1_3;
    wire                   awvalid_vect_1_3;
    wire                        awready_1_3;
    wire  [3:0]                 aw_qv_1_3;
   
    // Write Channel
    wire  [31:0]                wdata_1_3;
    wire  [3:0]                 wstrb_1_3;
    wire                        wlast_1_3;
    wire                        wvalid_1_3;
    wire                        wready_1_3;

    // Write Response Channel
    wire  [3:0]                 bid_1_3;
    wire  [1:0]                 bresp_1_3;
    wire                        bvalid_1_3;
    wire                        bready_1_3;

    // Read Address Channel
    wire  [3:0]                 aruser_1_3;
    wire  [3:0]                 arid_1_3;
    wire  [31:0]                araddr_1_3;
    wire  [7:0]                 arlen_1_3;
    wire  [2:0]                 arsize_1_3;
    wire  [1:0]                 arburst_1_3;
    wire                        arlock_1_3;
    wire  [3:0]                 arcache_1_3;
    wire  [2:0]                 arprot_1_3;
    wire                        arvalid_1_3;
    wire                   arvalid_vect_1_3;
    wire                        arready_1_3;
    wire  [3:0]                 ar_qv_1_3;
   
    // Read Channel
    wire  [3:0]                 rid_1_3;
    wire  [31:0]                rdata_1_3;
    wire  [1:0]                 rresp_1_3;
    wire                        rlast_1_3;
    wire                        rvalid_1_3;
    wire                        rready_1_3;


    // Connects SlaveInterface 1 to MasterInterface 6
    // Write Address Channel
    wire  [3:0]                 awuser_1_6;
    wire  [3:0]                 awid_1_6;
    wire  [31:0]                awaddr_1_6;
    wire  [7:0]                 awlen_1_6;
    wire  [2:0]                 awsize_1_6;
    wire  [1:0]                 awburst_1_6;
    wire                        awlock_1_6;
    wire  [3:0]                 awcache_1_6;
    wire  [2:0]                 awprot_1_6;
    wire                        awvalid_1_6;
    wire                   awvalid_vect_1_6;
    wire                        awready_1_6;
    wire  [3:0]                 aw_qv_1_6;
   
    // Write Channel
    wire  [31:0]                wdata_1_6;
    wire  [3:0]                 wstrb_1_6;
    wire                        wlast_1_6;
    wire                        wvalid_1_6;
    wire                        wready_1_6;

    // Write Response Channel
    wire  [3:0]                 bid_1_6;
    wire  [1:0]                 bresp_1_6;
    wire                        bvalid_1_6;
    wire                        bready_1_6;

    // Read Address Channel
    wire  [3:0]                 aruser_1_6;
    wire  [3:0]                 arid_1_6;
    wire  [31:0]                araddr_1_6;
    wire  [7:0]                 arlen_1_6;
    wire  [2:0]                 arsize_1_6;
    wire  [1:0]                 arburst_1_6;
    wire                        arlock_1_6;
    wire  [3:0]                 arcache_1_6;
    wire  [2:0]                 arprot_1_6;
    wire                        arvalid_1_6;
    wire                   arvalid_vect_1_6;
    wire                        arready_1_6;
    wire  [3:0]                 ar_qv_1_6;
   
    // Read Channel
    wire  [3:0]                 rid_1_6;
    wire  [31:0]                rdata_1_6;
    wire  [1:0]                 rresp_1_6;
    wire                        rlast_1_6;
    wire                        rvalid_1_6;
    wire                        rready_1_6;


    // Connects SlaveInterface 1 to MasterInterface 8
    // Write Address Channel
    wire  [3:0]                 awuser_1_8;
    wire  [3:0]                 awid_1_8;
    wire  [31:0]                awaddr_1_8;
    wire  [7:0]                 awlen_1_8;
    wire  [2:0]                 awsize_1_8;
    wire  [1:0]                 awburst_1_8;
    wire                        awlock_1_8;
    wire  [3:0]                 awcache_1_8;
    wire  [2:0]                 awprot_1_8;
    wire                        awvalid_1_8;
    wire                   awvalid_vect_1_8;
    wire                        awready_1_8;
    wire  [3:0]                 aw_qv_1_8;
   
    // Write Channel
    wire  [31:0]                wdata_1_8;
    wire  [3:0]                 wstrb_1_8;
    wire                        wlast_1_8;
    wire                        wvalid_1_8;
    wire                        wready_1_8;

    // Write Response Channel
    wire  [3:0]                 bid_1_8;
    wire  [1:0]                 bresp_1_8;
    wire                        bvalid_1_8;
    wire                        bready_1_8;

    // Read Address Channel
    wire  [3:0]                 aruser_1_8;
    wire  [3:0]                 arid_1_8;
    wire  [31:0]                araddr_1_8;
    wire  [7:0]                 arlen_1_8;
    wire  [2:0]                 arsize_1_8;
    wire  [1:0]                 arburst_1_8;
    wire                        arlock_1_8;
    wire  [3:0]                 arcache_1_8;
    wire  [2:0]                 arprot_1_8;
    wire                        arvalid_1_8;
    wire                   arvalid_vect_1_8;
    wire                        arready_1_8;
    wire  [3:0]                 ar_qv_1_8;
   
    // Read Channel
    wire  [3:0]                 rid_1_8;
    wire  [31:0]                rdata_1_8;
    wire  [1:0]                 rresp_1_8;
    wire                        rlast_1_8;
    wire                        rvalid_1_8;
    wire                        rready_1_8;

 

  // ---------------------------------------------------------------------------
  //  start of code
  // ---------------------------------------------------------------------------


  // Merging of region and user signals
  assign awuseri_axi_s_0 = awregion_axi_s_0;
  assign aruseri_axi_s_0 = arregion_axi_s_0;

  assign awuseri_axi_s_1 = awregion_axi_s_1;
  assign aruseri_axi_s_1 = arregion_axi_s_1;

  assign awregion_axi_m_0 = awuseri_axi_m_0[3:0];
  assign arregion_axi_m_0 = aruseri_axi_m_0[3:0];
  assign awregion_axi_m_1 = awuseri_axi_m_1[3:0];
  assign arregion_axi_m_1 = aruseri_axi_m_1[3:0];
  assign awregion_axi_m_5 = awuseri_axi_m_5[3:0];
  assign arregion_axi_m_5 = aruseri_axi_m_5[3:0];
  assign awregion_axi_m_6 = awuseri_axi_m_6[3:0];
  assign arregion_axi_m_6 = aruseri_axi_m_6[3:0];
  assign awregion_axi_m_7 = awuseri_axi_m_7[3:0];
  assign arregion_axi_m_7 = aruseri_axi_m_7[3:0];
  assign awregion_axi_m_8 = awuseri_axi_m_8[3:0];
  assign arregion_axi_m_8 = aruseri_axi_m_8[3:0];
  assign awregion_axi_m_9 = awuseri_axi_m_9[3:0];
  assign arregion_axi_m_9 = aruseri_axi_m_9[3:0];
  assign awregion_axi_m_4 = awuseri_axi_m_4[3:0];
  assign arregion_axi_m_4 = aruseri_axi_m_4[3:0];
  assign awregion_axi_m_2 = awuseri_axi_m_2[3:0];
  assign arregion_axi_m_2 = aruseri_axi_m_2[3:0];


  // Instantiate multi-layer build layer module 
  nic400_switch2_ml_build_ysyx_rv32 u_nic400_switch2_ml_build_ysyx_rv32
  (    
        // External AXI Connections 

        // SlaveInterface 0 (connects to MasterInterface axi_s_0)

        // Write Address Channel
        .awuser_s0       (awuseri_axi_s_0),
        .awid_s0         (awid_axi_s_0),
        .awaddr_s0       (awaddr_axi_s_0),
        .awlen_s0        (awlen_axi_s_0),
        .awsize_s0       (awsize_axi_s_0),
        .awburst_s0      (awburst_axi_s_0),
        .awlock_s0       (awlock_axi_s_0),
        .awcache_s0      (awcache_axi_s_0),
        .awprot_s0       (awprot_axi_s_0),
        .awvalid_s0      (awvalid_axi_s_0),
        .awvalid_vect_s0 (awvalid_vect_axi_s_0),
        .awready_s0      (awready_axi_s_0),
        .aw_qv_s0        (aw_qv_axi_s_0),

        // Write Channel
        .wdata_s0        (wdata_axi_s_0),
        .wstrb_s0        (wstrb_axi_s_0),   
        .wlast_s0        (wlast_axi_s_0),
        .wvalid_s0       (wvalid_axi_s_0),
        .wready_s0       (wready_axi_s_0),

        // Write Response Channel
        .bid_s0          (bid_axi_s_0),
        .bresp_s0        (bresp_axi_s_0),
        .bvalid_s0       (bvalid_axi_s_0),
        .bready_s0       (bready_axi_s_0),  

        // Read Address Channel
        .aruser_s0       (aruseri_axi_s_0),
        .arid_s0         (arid_axi_s_0),
        .araddr_s0       (araddr_axi_s_0),
        .arlen_s0        (arlen_axi_s_0),
        .arsize_s0       (arsize_axi_s_0),
        .arburst_s0      (arburst_axi_s_0),
        .arlock_s0       (arlock_axi_s_0),
        .arcache_s0      (arcache_axi_s_0),
        .arprot_s0       (arprot_axi_s_0),
        .arvalid_s0      (arvalid_axi_s_0),
        .arvalid_vect_s0 (arvalid_vect_axi_s_0),
        .arready_s0      (arready_axi_s_0),
        .ar_qv_s0        (ar_qv_axi_s_0),
   
        // Read Channel
        .rid_s0          (rid_axi_s_0),
        .rdata_s0        (rdata_axi_s_0),
        .rresp_s0        (rresp_axi_s_0),
        .rlast_s0        (rlast_axi_s_0),
        .rvalid_s0       (rvalid_axi_s_0),
        .rready_s0       (rready_axi_s_0),

        // SlaveInterface 1 (connects to MasterInterface axi_s_1)

        // Write Address Channel
        .awuser_s1       (awuseri_axi_s_1),
        .awid_s1         (awid_axi_s_1),
        .awaddr_s1       (awaddr_axi_s_1),
        .awlen_s1        (awlen_axi_s_1),
        .awsize_s1       (awsize_axi_s_1),
        .awburst_s1      (awburst_axi_s_1),
        .awlock_s1       (awlock_axi_s_1),
        .awcache_s1      (awcache_axi_s_1),
        .awprot_s1       (awprot_axi_s_1),
        .awvalid_s1      (awvalid_axi_s_1),
        .awvalid_vect_s1 (awvalid_vect_axi_s_1),
        .awready_s1      (awready_axi_s_1),
        .aw_qv_s1        (aw_qv_axi_s_1),

        // Write Channel
        .wdata_s1        (wdata_axi_s_1),
        .wstrb_s1        (wstrb_axi_s_1),   
        .wlast_s1        (wlast_axi_s_1),
        .wvalid_s1       (wvalid_axi_s_1),
        .wready_s1       (wready_axi_s_1),

        // Write Response Channel
        .bid_s1          (bid_axi_s_1),
        .bresp_s1        (bresp_axi_s_1),
        .bvalid_s1       (bvalid_axi_s_1),
        .bready_s1       (bready_axi_s_1),  

        // Read Address Channel
        .aruser_s1       (aruseri_axi_s_1),
        .arid_s1         (arid_axi_s_1),
        .araddr_s1       (araddr_axi_s_1),
        .arlen_s1        (arlen_axi_s_1),
        .arsize_s1       (arsize_axi_s_1),
        .arburst_s1      (arburst_axi_s_1),
        .arlock_s1       (arlock_axi_s_1),
        .arcache_s1      (arcache_axi_s_1),
        .arprot_s1       (arprot_axi_s_1),
        .arvalid_s1      (arvalid_axi_s_1),
        .arvalid_vect_s1 (arvalid_vect_axi_s_1),
        .arready_s1      (arready_axi_s_1),
        .ar_qv_s1        (ar_qv_axi_s_1),
   
        // Read Channel
        .rid_s1          (rid_axi_s_1),
        .rdata_s1        (rdata_axi_s_1),
        .rresp_s1        (rresp_axi_s_1),
        .rlast_s1        (rlast_axi_s_1),
        .rvalid_s1       (rvalid_axi_s_1),
        .rready_s1       (rready_axi_s_1),


        // Internal AXI Connections 

        // Connects SlaveInterface 0 to MasterInterface 0
        // Write Address Channel
        .awuser_0_0       (awuser_0_0),
        .awid_0_0         (awid_0_0),
        .awaddr_0_0       (awaddr_0_0),
        .awlen_0_0        (awlen_0_0),
        .awsize_0_0       (awsize_0_0),
        .awburst_0_0      (awburst_0_0),
        .awlock_0_0       (awlock_0_0),
        .awcache_0_0      (awcache_0_0),
        .awprot_0_0       (awprot_0_0),
        .awvalid_0_0      (awvalid_0_0),
        .awvalid_vect_0_0 (awvalid_vect_0_0),
        .awready_0_0      (awready_0_0),
        .aw_qv_0_0        (aw_qv_0_0),
   
        // Write Channel
        .wdata_0_0        (wdata_0_0),
        .wstrb_0_0        (wstrb_0_0),   
        .wlast_0_0        (wlast_0_0),
        .wvalid_0_0       (wvalid_0_0),
        .wready_0_0       (wready_0_0),

        // Write Response Channel
        .bid_0_0          (bid_0_0),
        .bresp_0_0        (bresp_0_0),
        .bvalid_0_0       (bvalid_0_0),
        .bready_0_0       (bready_0_0),  

        // Read Address Channel
        .aruser_0_0       (aruser_0_0),
        .arid_0_0         (arid_0_0),
        .araddr_0_0       (araddr_0_0),
        .arlen_0_0        (arlen_0_0),
        .arsize_0_0       (arsize_0_0),
        .arburst_0_0      (arburst_0_0),
        .arlock_0_0       (arlock_0_0),
        .arcache_0_0      (arcache_0_0),
        .arprot_0_0       (arprot_0_0),
        .arvalid_0_0      (arvalid_0_0),
        .arvalid_vect_0_0 (arvalid_vect_0_0),
        .arready_0_0      (arready_0_0),
        .ar_qv_0_0        (ar_qv_0_0),
   
        // Read Channel
        .rid_0_0          (rid_0_0),
        .rdata_0_0        (rdata_0_0),
        .rresp_0_0        (rresp_0_0),
        .rlast_0_0        (rlast_0_0),
        .rvalid_0_0       (rvalid_0_0),
        .rready_0_0       (rready_0_0),


        // Connects SlaveInterface 0 to MasterInterface 1
        // Write Address Channel
        .awuser_0_1       (awuser_0_1),
        .awid_0_1         (awid_0_1),
        .awaddr_0_1       (awaddr_0_1),
        .awlen_0_1        (awlen_0_1),
        .awsize_0_1       (awsize_0_1),
        .awburst_0_1      (awburst_0_1),
        .awlock_0_1       (awlock_0_1),
        .awcache_0_1      (awcache_0_1),
        .awprot_0_1       (awprot_0_1),
        .awvalid_0_1      (awvalid_0_1),
        .awvalid_vect_0_1 (awvalid_vect_0_1),
        .awready_0_1      (awready_0_1),
        .aw_qv_0_1        (aw_qv_0_1),
   
        // Write Channel
        .wdata_0_1        (wdata_0_1),
        .wstrb_0_1        (wstrb_0_1),   
        .wlast_0_1        (wlast_0_1),
        .wvalid_0_1       (wvalid_0_1),
        .wready_0_1       (wready_0_1),

        // Write Response Channel
        .bid_0_1          (bid_0_1),
        .bresp_0_1        (bresp_0_1),
        .bvalid_0_1       (bvalid_0_1),
        .bready_0_1       (bready_0_1),  

        // Read Address Channel
        .aruser_0_1       (aruser_0_1),
        .arid_0_1         (arid_0_1),
        .araddr_0_1       (araddr_0_1),
        .arlen_0_1        (arlen_0_1),
        .arsize_0_1       (arsize_0_1),
        .arburst_0_1      (arburst_0_1),
        .arlock_0_1       (arlock_0_1),
        .arcache_0_1      (arcache_0_1),
        .arprot_0_1       (arprot_0_1),
        .arvalid_0_1      (arvalid_0_1),
        .arvalid_vect_0_1 (arvalid_vect_0_1),
        .arready_0_1      (arready_0_1),
        .ar_qv_0_1        (ar_qv_0_1),
   
        // Read Channel
        .rid_0_1          (rid_0_1),
        .rdata_0_1        (rdata_0_1),
        .rresp_0_1        (rresp_0_1),
        .rlast_0_1        (rlast_0_1),
        .rvalid_0_1       (rvalid_0_1),
        .rready_0_1       (rready_0_1),


        // Connects SlaveInterface 0 to MasterInterface 2
        // Write Address Channel
        .awuser_0_2       (awuser_0_2),
        .awid_0_2         (awid_0_2),
        .awaddr_0_2       (awaddr_0_2),
        .awlen_0_2        (awlen_0_2),
        .awsize_0_2       (awsize_0_2),
        .awburst_0_2      (awburst_0_2),
        .awlock_0_2       (awlock_0_2),
        .awcache_0_2      (awcache_0_2),
        .awprot_0_2       (awprot_0_2),
        .awvalid_0_2      (awvalid_0_2),
        .awvalid_vect_0_2 (awvalid_vect_0_2),
        .awready_0_2      (awready_0_2),
        .aw_qv_0_2        (aw_qv_0_2),
   
        // Write Channel
        .wdata_0_2        (wdata_0_2),
        .wstrb_0_2        (wstrb_0_2),   
        .wlast_0_2        (wlast_0_2),
        .wvalid_0_2       (wvalid_0_2),
        .wready_0_2       (wready_0_2),

        // Write Response Channel
        .bid_0_2          (bid_0_2),
        .bresp_0_2        (bresp_0_2),
        .bvalid_0_2       (bvalid_0_2),
        .bready_0_2       (bready_0_2),  

        // Read Address Channel
        .aruser_0_2       (aruser_0_2),
        .arid_0_2         (arid_0_2),
        .araddr_0_2       (araddr_0_2),
        .arlen_0_2        (arlen_0_2),
        .arsize_0_2       (arsize_0_2),
        .arburst_0_2      (arburst_0_2),
        .arlock_0_2       (arlock_0_2),
        .arcache_0_2      (arcache_0_2),
        .arprot_0_2       (arprot_0_2),
        .arvalid_0_2      (arvalid_0_2),
        .arvalid_vect_0_2 (arvalid_vect_0_2),
        .arready_0_2      (arready_0_2),
        .ar_qv_0_2        (ar_qv_0_2),
   
        // Read Channel
        .rid_0_2          (rid_0_2),
        .rdata_0_2        (rdata_0_2),
        .rresp_0_2        (rresp_0_2),
        .rlast_0_2        (rlast_0_2),
        .rvalid_0_2       (rvalid_0_2),
        .rready_0_2       (rready_0_2),


        // Connects SlaveInterface 0 to MasterInterface 3
        // Write Address Channel
        .awuser_0_3       (awuser_0_3),
        .awid_0_3         (awid_0_3),
        .awaddr_0_3       (awaddr_0_3),
        .awlen_0_3        (awlen_0_3),
        .awsize_0_3       (awsize_0_3),
        .awburst_0_3      (awburst_0_3),
        .awlock_0_3       (awlock_0_3),
        .awcache_0_3      (awcache_0_3),
        .awprot_0_3       (awprot_0_3),
        .awvalid_0_3      (awvalid_0_3),
        .awvalid_vect_0_3 (awvalid_vect_0_3),
        .awready_0_3      (awready_0_3),
        .aw_qv_0_3        (aw_qv_0_3),
   
        // Write Channel
        .wdata_0_3        (wdata_0_3),
        .wstrb_0_3        (wstrb_0_3),   
        .wlast_0_3        (wlast_0_3),
        .wvalid_0_3       (wvalid_0_3),
        .wready_0_3       (wready_0_3),

        // Write Response Channel
        .bid_0_3          (bid_0_3),
        .bresp_0_3        (bresp_0_3),
        .bvalid_0_3       (bvalid_0_3),
        .bready_0_3       (bready_0_3),  

        // Read Address Channel
        .aruser_0_3       (aruser_0_3),
        .arid_0_3         (arid_0_3),
        .araddr_0_3       (araddr_0_3),
        .arlen_0_3        (arlen_0_3),
        .arsize_0_3       (arsize_0_3),
        .arburst_0_3      (arburst_0_3),
        .arlock_0_3       (arlock_0_3),
        .arcache_0_3      (arcache_0_3),
        .arprot_0_3       (arprot_0_3),
        .arvalid_0_3      (arvalid_0_3),
        .arvalid_vect_0_3 (arvalid_vect_0_3),
        .arready_0_3      (arready_0_3),
        .ar_qv_0_3        (ar_qv_0_3),
   
        // Read Channel
        .rid_0_3          (rid_0_3),
        .rdata_0_3        (rdata_0_3),
        .rresp_0_3        (rresp_0_3),
        .rlast_0_3        (rlast_0_3),
        .rvalid_0_3       (rvalid_0_3),
        .rready_0_3       (rready_0_3),


        // Connects SlaveInterface 0 to MasterInterface 4
        // Write Address Channel
        .awuser_0_4       (awuser_0_4),
        .awid_0_4         (awid_0_4),
        .awaddr_0_4       (awaddr_0_4),
        .awlen_0_4        (awlen_0_4),
        .awsize_0_4       (awsize_0_4),
        .awburst_0_4      (awburst_0_4),
        .awlock_0_4       (awlock_0_4),
        .awcache_0_4      (awcache_0_4),
        .awprot_0_4       (awprot_0_4),
        .awvalid_0_4      (awvalid_0_4),
        .awvalid_vect_0_4 (awvalid_vect_0_4),
        .awready_0_4      (awready_0_4),
        .aw_qv_0_4        (aw_qv_0_4),
   
        // Write Channel
        .wdata_0_4        (wdata_0_4),
        .wstrb_0_4        (wstrb_0_4),   
        .wlast_0_4        (wlast_0_4),
        .wvalid_0_4       (wvalid_0_4),
        .wready_0_4       (wready_0_4),

        // Write Response Channel
        .bid_0_4          (bid_0_4),
        .bresp_0_4        (bresp_0_4),
        .bvalid_0_4       (bvalid_0_4),
        .bready_0_4       (bready_0_4),  

        // Read Address Channel
        .aruser_0_4       (aruser_0_4),
        .arid_0_4         (arid_0_4),
        .araddr_0_4       (araddr_0_4),
        .arlen_0_4        (arlen_0_4),
        .arsize_0_4       (arsize_0_4),
        .arburst_0_4      (arburst_0_4),
        .arlock_0_4       (arlock_0_4),
        .arcache_0_4      (arcache_0_4),
        .arprot_0_4       (arprot_0_4),
        .arvalid_0_4      (arvalid_0_4),
        .arvalid_vect_0_4 (arvalid_vect_0_4),
        .arready_0_4      (arready_0_4),
        .ar_qv_0_4        (ar_qv_0_4),
   
        // Read Channel
        .rid_0_4          (rid_0_4),
        .rdata_0_4        (rdata_0_4),
        .rresp_0_4        (rresp_0_4),
        .rlast_0_4        (rlast_0_4),
        .rvalid_0_4       (rvalid_0_4),
        .rready_0_4       (rready_0_4),


        // Connects SlaveInterface 0 to MasterInterface 5
        // Write Address Channel
        .awuser_0_5       (awuser_0_5),
        .awid_0_5         (awid_0_5),
        .awaddr_0_5       (awaddr_0_5),
        .awlen_0_5        (awlen_0_5),
        .awsize_0_5       (awsize_0_5),
        .awburst_0_5      (awburst_0_5),
        .awlock_0_5       (awlock_0_5),
        .awcache_0_5      (awcache_0_5),
        .awprot_0_5       (awprot_0_5),
        .awvalid_0_5      (awvalid_0_5),
        .awvalid_vect_0_5 (awvalid_vect_0_5),
        .awready_0_5      (awready_0_5),
        .aw_qv_0_5        (aw_qv_0_5),
   
        // Write Channel
        .wdata_0_5        (wdata_0_5),
        .wstrb_0_5        (wstrb_0_5),   
        .wlast_0_5        (wlast_0_5),
        .wvalid_0_5       (wvalid_0_5),
        .wready_0_5       (wready_0_5),

        // Write Response Channel
        .bid_0_5          (bid_0_5),
        .bresp_0_5        (bresp_0_5),
        .bvalid_0_5       (bvalid_0_5),
        .bready_0_5       (bready_0_5),  

        // Read Address Channel
        .aruser_0_5       (aruser_0_5),
        .arid_0_5         (arid_0_5),
        .araddr_0_5       (araddr_0_5),
        .arlen_0_5        (arlen_0_5),
        .arsize_0_5       (arsize_0_5),
        .arburst_0_5      (arburst_0_5),
        .arlock_0_5       (arlock_0_5),
        .arcache_0_5      (arcache_0_5),
        .arprot_0_5       (arprot_0_5),
        .arvalid_0_5      (arvalid_0_5),
        .arvalid_vect_0_5 (arvalid_vect_0_5),
        .arready_0_5      (arready_0_5),
        .ar_qv_0_5        (ar_qv_0_5),
   
        // Read Channel
        .rid_0_5          (rid_0_5),
        .rdata_0_5        (rdata_0_5),
        .rresp_0_5        (rresp_0_5),
        .rlast_0_5        (rlast_0_5),
        .rvalid_0_5       (rvalid_0_5),
        .rready_0_5       (rready_0_5),


        // Connects SlaveInterface 0 to MasterInterface 6
        // Write Address Channel
        .awuser_0_6       (awuser_0_6),
        .awid_0_6         (awid_0_6),
        .awaddr_0_6       (awaddr_0_6),
        .awlen_0_6        (awlen_0_6),
        .awsize_0_6       (awsize_0_6),
        .awburst_0_6      (awburst_0_6),
        .awlock_0_6       (awlock_0_6),
        .awcache_0_6      (awcache_0_6),
        .awprot_0_6       (awprot_0_6),
        .awvalid_0_6      (awvalid_0_6),
        .awvalid_vect_0_6 (awvalid_vect_0_6),
        .awready_0_6      (awready_0_6),
        .aw_qv_0_6        (aw_qv_0_6),
   
        // Write Channel
        .wdata_0_6        (wdata_0_6),
        .wstrb_0_6        (wstrb_0_6),   
        .wlast_0_6        (wlast_0_6),
        .wvalid_0_6       (wvalid_0_6),
        .wready_0_6       (wready_0_6),

        // Write Response Channel
        .bid_0_6          (bid_0_6),
        .bresp_0_6        (bresp_0_6),
        .bvalid_0_6       (bvalid_0_6),
        .bready_0_6       (bready_0_6),  

        // Read Address Channel
        .aruser_0_6       (aruser_0_6),
        .arid_0_6         (arid_0_6),
        .araddr_0_6       (araddr_0_6),
        .arlen_0_6        (arlen_0_6),
        .arsize_0_6       (arsize_0_6),
        .arburst_0_6      (arburst_0_6),
        .arlock_0_6       (arlock_0_6),
        .arcache_0_6      (arcache_0_6),
        .arprot_0_6       (arprot_0_6),
        .arvalid_0_6      (arvalid_0_6),
        .arvalid_vect_0_6 (arvalid_vect_0_6),
        .arready_0_6      (arready_0_6),
        .ar_qv_0_6        (ar_qv_0_6),
   
        // Read Channel
        .rid_0_6          (rid_0_6),
        .rdata_0_6        (rdata_0_6),
        .rresp_0_6        (rresp_0_6),
        .rlast_0_6        (rlast_0_6),
        .rvalid_0_6       (rvalid_0_6),
        .rready_0_6       (rready_0_6),


        // Connects SlaveInterface 0 to MasterInterface 7
        // Write Address Channel
        .awuser_0_7       (awuser_0_7),
        .awid_0_7         (awid_0_7),
        .awaddr_0_7       (awaddr_0_7),
        .awlen_0_7        (awlen_0_7),
        .awsize_0_7       (awsize_0_7),
        .awburst_0_7      (awburst_0_7),
        .awlock_0_7       (awlock_0_7),
        .awcache_0_7      (awcache_0_7),
        .awprot_0_7       (awprot_0_7),
        .awvalid_0_7      (awvalid_0_7),
        .awvalid_vect_0_7 (awvalid_vect_0_7),
        .awready_0_7      (awready_0_7),
        .aw_qv_0_7        (aw_qv_0_7),
   
        // Write Channel
        .wdata_0_7        (wdata_0_7),
        .wstrb_0_7        (wstrb_0_7),   
        .wlast_0_7        (wlast_0_7),
        .wvalid_0_7       (wvalid_0_7),
        .wready_0_7       (wready_0_7),

        // Write Response Channel
        .bid_0_7          (bid_0_7),
        .bresp_0_7        (bresp_0_7),
        .bvalid_0_7       (bvalid_0_7),
        .bready_0_7       (bready_0_7),  

        // Read Address Channel
        .aruser_0_7       (aruser_0_7),
        .arid_0_7         (arid_0_7),
        .araddr_0_7       (araddr_0_7),
        .arlen_0_7        (arlen_0_7),
        .arsize_0_7       (arsize_0_7),
        .arburst_0_7      (arburst_0_7),
        .arlock_0_7       (arlock_0_7),
        .arcache_0_7      (arcache_0_7),
        .arprot_0_7       (arprot_0_7),
        .arvalid_0_7      (arvalid_0_7),
        .arvalid_vect_0_7 (arvalid_vect_0_7),
        .arready_0_7      (arready_0_7),
        .ar_qv_0_7        (ar_qv_0_7),
   
        // Read Channel
        .rid_0_7          (rid_0_7),
        .rdata_0_7        (rdata_0_7),
        .rresp_0_7        (rresp_0_7),
        .rlast_0_7        (rlast_0_7),
        .rvalid_0_7       (rvalid_0_7),
        .rready_0_7       (rready_0_7),


        // Connects SlaveInterface 0 to MasterInterface 8
        // Write Address Channel
        .awuser_0_8       (awuser_0_8),
        .awid_0_8         (awid_0_8),
        .awaddr_0_8       (awaddr_0_8),
        .awlen_0_8        (awlen_0_8),
        .awsize_0_8       (awsize_0_8),
        .awburst_0_8      (awburst_0_8),
        .awlock_0_8       (awlock_0_8),
        .awcache_0_8      (awcache_0_8),
        .awprot_0_8       (awprot_0_8),
        .awvalid_0_8      (awvalid_0_8),
        .awvalid_vect_0_8 (awvalid_vect_0_8),
        .awready_0_8      (awready_0_8),
        .aw_qv_0_8        (aw_qv_0_8),
   
        // Write Channel
        .wdata_0_8        (wdata_0_8),
        .wstrb_0_8        (wstrb_0_8),   
        .wlast_0_8        (wlast_0_8),
        .wvalid_0_8       (wvalid_0_8),
        .wready_0_8       (wready_0_8),

        // Write Response Channel
        .bid_0_8          (bid_0_8),
        .bresp_0_8        (bresp_0_8),
        .bvalid_0_8       (bvalid_0_8),
        .bready_0_8       (bready_0_8),  

        // Read Address Channel
        .aruser_0_8       (aruser_0_8),
        .arid_0_8         (arid_0_8),
        .araddr_0_8       (araddr_0_8),
        .arlen_0_8        (arlen_0_8),
        .arsize_0_8       (arsize_0_8),
        .arburst_0_8      (arburst_0_8),
        .arlock_0_8       (arlock_0_8),
        .arcache_0_8      (arcache_0_8),
        .arprot_0_8       (arprot_0_8),
        .arvalid_0_8      (arvalid_0_8),
        .arvalid_vect_0_8 (arvalid_vect_0_8),
        .arready_0_8      (arready_0_8),
        .ar_qv_0_8        (ar_qv_0_8),
   
        // Read Channel
        .rid_0_8          (rid_0_8),
        .rdata_0_8        (rdata_0_8),
        .rresp_0_8        (rresp_0_8),
        .rlast_0_8        (rlast_0_8),
        .rvalid_0_8       (rvalid_0_8),
        .rready_0_8       (rready_0_8),


        // Connects SlaveInterface 1 to MasterInterface 2
        // Write Address Channel
        .awuser_1_2       (awuser_1_2),
        .awid_1_2         (awid_1_2),
        .awaddr_1_2       (awaddr_1_2),
        .awlen_1_2        (awlen_1_2),
        .awsize_1_2       (awsize_1_2),
        .awburst_1_2      (awburst_1_2),
        .awlock_1_2       (awlock_1_2),
        .awcache_1_2      (awcache_1_2),
        .awprot_1_2       (awprot_1_2),
        .awvalid_1_2      (awvalid_1_2),
        .awvalid_vect_1_2 (awvalid_vect_1_2),
        .awready_1_2      (awready_1_2),
        .aw_qv_1_2        (aw_qv_1_2),
   
        // Write Channel
        .wdata_1_2        (wdata_1_2),
        .wstrb_1_2        (wstrb_1_2),   
        .wlast_1_2        (wlast_1_2),
        .wvalid_1_2       (wvalid_1_2),
        .wready_1_2       (wready_1_2),

        // Write Response Channel
        .bid_1_2          (bid_1_2),
        .bresp_1_2        (bresp_1_2),
        .bvalid_1_2       (bvalid_1_2),
        .bready_1_2       (bready_1_2),  

        // Read Address Channel
        .aruser_1_2       (aruser_1_2),
        .arid_1_2         (arid_1_2),
        .araddr_1_2       (araddr_1_2),
        .arlen_1_2        (arlen_1_2),
        .arsize_1_2       (arsize_1_2),
        .arburst_1_2      (arburst_1_2),
        .arlock_1_2       (arlock_1_2),
        .arcache_1_2      (arcache_1_2),
        .arprot_1_2       (arprot_1_2),
        .arvalid_1_2      (arvalid_1_2),
        .arvalid_vect_1_2 (arvalid_vect_1_2),
        .arready_1_2      (arready_1_2),
        .ar_qv_1_2        (ar_qv_1_2),
   
        // Read Channel
        .rid_1_2          (rid_1_2),
        .rdata_1_2        (rdata_1_2),
        .rresp_1_2        (rresp_1_2),
        .rlast_1_2        (rlast_1_2),
        .rvalid_1_2       (rvalid_1_2),
        .rready_1_2       (rready_1_2),


        // Connects SlaveInterface 1 to MasterInterface 3
        // Write Address Channel
        .awuser_1_3       (awuser_1_3),
        .awid_1_3         (awid_1_3),
        .awaddr_1_3       (awaddr_1_3),
        .awlen_1_3        (awlen_1_3),
        .awsize_1_3       (awsize_1_3),
        .awburst_1_3      (awburst_1_3),
        .awlock_1_3       (awlock_1_3),
        .awcache_1_3      (awcache_1_3),
        .awprot_1_3       (awprot_1_3),
        .awvalid_1_3      (awvalid_1_3),
        .awvalid_vect_1_3 (awvalid_vect_1_3),
        .awready_1_3      (awready_1_3),
        .aw_qv_1_3        (aw_qv_1_3),
   
        // Write Channel
        .wdata_1_3        (wdata_1_3),
        .wstrb_1_3        (wstrb_1_3),   
        .wlast_1_3        (wlast_1_3),
        .wvalid_1_3       (wvalid_1_3),
        .wready_1_3       (wready_1_3),

        // Write Response Channel
        .bid_1_3          (bid_1_3),
        .bresp_1_3        (bresp_1_3),
        .bvalid_1_3       (bvalid_1_3),
        .bready_1_3       (bready_1_3),  

        // Read Address Channel
        .aruser_1_3       (aruser_1_3),
        .arid_1_3         (arid_1_3),
        .araddr_1_3       (araddr_1_3),
        .arlen_1_3        (arlen_1_3),
        .arsize_1_3       (arsize_1_3),
        .arburst_1_3      (arburst_1_3),
        .arlock_1_3       (arlock_1_3),
        .arcache_1_3      (arcache_1_3),
        .arprot_1_3       (arprot_1_3),
        .arvalid_1_3      (arvalid_1_3),
        .arvalid_vect_1_3 (arvalid_vect_1_3),
        .arready_1_3      (arready_1_3),
        .ar_qv_1_3        (ar_qv_1_3),
   
        // Read Channel
        .rid_1_3          (rid_1_3),
        .rdata_1_3        (rdata_1_3),
        .rresp_1_3        (rresp_1_3),
        .rlast_1_3        (rlast_1_3),
        .rvalid_1_3       (rvalid_1_3),
        .rready_1_3       (rready_1_3),


        // Connects SlaveInterface 1 to MasterInterface 6
        // Write Address Channel
        .awuser_1_6       (awuser_1_6),
        .awid_1_6         (awid_1_6),
        .awaddr_1_6       (awaddr_1_6),
        .awlen_1_6        (awlen_1_6),
        .awsize_1_6       (awsize_1_6),
        .awburst_1_6      (awburst_1_6),
        .awlock_1_6       (awlock_1_6),
        .awcache_1_6      (awcache_1_6),
        .awprot_1_6       (awprot_1_6),
        .awvalid_1_6      (awvalid_1_6),
        .awvalid_vect_1_6 (awvalid_vect_1_6),
        .awready_1_6      (awready_1_6),
        .aw_qv_1_6        (aw_qv_1_6),
   
        // Write Channel
        .wdata_1_6        (wdata_1_6),
        .wstrb_1_6        (wstrb_1_6),   
        .wlast_1_6        (wlast_1_6),
        .wvalid_1_6       (wvalid_1_6),
        .wready_1_6       (wready_1_6),

        // Write Response Channel
        .bid_1_6          (bid_1_6),
        .bresp_1_6        (bresp_1_6),
        .bvalid_1_6       (bvalid_1_6),
        .bready_1_6       (bready_1_6),  

        // Read Address Channel
        .aruser_1_6       (aruser_1_6),
        .arid_1_6         (arid_1_6),
        .araddr_1_6       (araddr_1_6),
        .arlen_1_6        (arlen_1_6),
        .arsize_1_6       (arsize_1_6),
        .arburst_1_6      (arburst_1_6),
        .arlock_1_6       (arlock_1_6),
        .arcache_1_6      (arcache_1_6),
        .arprot_1_6       (arprot_1_6),
        .arvalid_1_6      (arvalid_1_6),
        .arvalid_vect_1_6 (arvalid_vect_1_6),
        .arready_1_6      (arready_1_6),
        .ar_qv_1_6        (ar_qv_1_6),
   
        // Read Channel
        .rid_1_6          (rid_1_6),
        .rdata_1_6        (rdata_1_6),
        .rresp_1_6        (rresp_1_6),
        .rlast_1_6        (rlast_1_6),
        .rvalid_1_6       (rvalid_1_6),
        .rready_1_6       (rready_1_6),


        // Connects SlaveInterface 1 to MasterInterface 8
        // Write Address Channel
        .awuser_1_8       (awuser_1_8),
        .awid_1_8         (awid_1_8),
        .awaddr_1_8       (awaddr_1_8),
        .awlen_1_8        (awlen_1_8),
        .awsize_1_8       (awsize_1_8),
        .awburst_1_8      (awburst_1_8),
        .awlock_1_8       (awlock_1_8),
        .awcache_1_8      (awcache_1_8),
        .awprot_1_8       (awprot_1_8),
        .awvalid_1_8      (awvalid_1_8),
        .awvalid_vect_1_8 (awvalid_vect_1_8),
        .awready_1_8      (awready_1_8),
        .aw_qv_1_8        (aw_qv_1_8),
   
        // Write Channel
        .wdata_1_8        (wdata_1_8),
        .wstrb_1_8        (wstrb_1_8),   
        .wlast_1_8        (wlast_1_8),
        .wvalid_1_8       (wvalid_1_8),
        .wready_1_8       (wready_1_8),

        // Write Response Channel
        .bid_1_8          (bid_1_8),
        .bresp_1_8        (bresp_1_8),
        .bvalid_1_8       (bvalid_1_8),
        .bready_1_8       (bready_1_8),  

        // Read Address Channel
        .aruser_1_8       (aruser_1_8),
        .arid_1_8         (arid_1_8),
        .araddr_1_8       (araddr_1_8),
        .arlen_1_8        (arlen_1_8),
        .arsize_1_8       (arsize_1_8),
        .arburst_1_8      (arburst_1_8),
        .arlock_1_8       (arlock_1_8),
        .arcache_1_8      (arcache_1_8),
        .arprot_1_8       (arprot_1_8),
        .arvalid_1_8      (arvalid_1_8),
        .arvalid_vect_1_8 (arvalid_vect_1_8),
        .arready_1_8      (arready_1_8),
        .ar_qv_1_8        (ar_qv_1_8),
   
        // Read Channel
        .rid_1_8          (rid_1_8),
        .rdata_1_8        (rdata_1_8),
        .rresp_1_8        (rresp_1_8),
        .rlast_1_8        (rlast_1_8),
        .rvalid_1_8       (rvalid_1_8),
        .rready_1_8       (rready_1_8),


        // Miscelaneous connections
        .aclk    (aclk),
        .aresetn    (aresetn)
  );





  // Instantiate multi-layer map layer module 
  nic400_switch2_ml_map_ysyx_rv32 u_nic400_switch2_ml_map_ysyx_rv32
  (     
        // External AXI Connections 

        // MasterInterface 0 (connects to Slave axi_m_0)
        // Write Address Channel
        .awuser_m0       (awuseri_axi_m_0),
        .awid_m0         (awid_axi_m_0),
        .awaddr_m0       (awaddr_axi_m_0),
        .awlen_m0        (awlen_axi_m_0),
        .awsize_m0       (awsize_axi_m_0),
        .awburst_m0      (awburst_axi_m_0),
        .awlock_m0       (awlock_axi_m_0),
        .awcache_m0      (awcache_axi_m_0),
        .awprot_m0       (awprot_axi_m_0),
        .awvalid_m0      (awvalid_axi_m_0),
        .awvalid_vect_m0 (awvalid_vect_axi_m_0),
        .awready_m0      (awready_axi_m_0),
        .aw_qv_m0        (aw_qv_axi_m_0),
   
        // Write Channel
        .wdata_m0        (wdata_axi_m_0),
        .wstrb_m0        (wstrb_axi_m_0),   
        .wlast_m0        (wlast_axi_m_0),
        .wvalid_m0       (wvalid_axi_m_0),
        .wready_m0       (wready_axi_m_0),

        // Write Response Channel
        .bid_m0          (bid_axi_m_0),
        .bresp_m0        (bresp_axi_m_0),
        .bvalid_m0       (bvalid_axi_m_0),
        .bready_m0       (bready_axi_m_0),  

        // Read Address Channel
        .aruser_m0       (aruseri_axi_m_0),
        .arid_m0         (arid_axi_m_0),
        .araddr_m0       (araddr_axi_m_0),
        .arlen_m0        (arlen_axi_m_0),
        .arsize_m0       (arsize_axi_m_0),
        .arburst_m0      (arburst_axi_m_0),
        .arlock_m0       (arlock_axi_m_0),
        .arcache_m0      (arcache_axi_m_0),
        .arprot_m0       (arprot_axi_m_0),
        .arvalid_m0      (arvalid_axi_m_0),
        .arvalid_vect_m0 (arvalid_vect_axi_m_0),
        .arready_m0      (arready_axi_m_0),
        .ar_qv_m0        (ar_qv_axi_m_0),
   
        // Read Channel
        .rid_m0          (rid_axi_m_0),
        .rdata_m0        (rdata_axi_m_0),
        .rresp_m0        (rresp_axi_m_0),
        .rlast_m0        (rlast_axi_m_0),
        .rvalid_m0       (rvalid_axi_m_0),
        .rready_m0       (rready_axi_m_0),

        // MasterInterface 1 (connects to Slave axi_m_1)
        // Write Address Channel
        .awuser_m1       (awuseri_axi_m_1),
        .awid_m1         (awid_axi_m_1),
        .awaddr_m1       (awaddr_axi_m_1),
        .awlen_m1        (awlen_axi_m_1),
        .awsize_m1       (awsize_axi_m_1),
        .awburst_m1      (awburst_axi_m_1),
        .awlock_m1       (awlock_axi_m_1),
        .awcache_m1      (awcache_axi_m_1),
        .awprot_m1       (awprot_axi_m_1),
        .awvalid_m1      (awvalid_axi_m_1),
        .awvalid_vect_m1 (awvalid_vect_axi_m_1),
        .awready_m1      (awready_axi_m_1),
        .aw_qv_m1        (aw_qv_axi_m_1),
   
        // Write Channel
        .wdata_m1        (wdata_axi_m_1),
        .wstrb_m1        (wstrb_axi_m_1),   
        .wlast_m1        (wlast_axi_m_1),
        .wvalid_m1       (wvalid_axi_m_1),
        .wready_m1       (wready_axi_m_1),

        // Write Response Channel
        .bid_m1          (bid_axi_m_1),
        .bresp_m1        (bresp_axi_m_1),
        .bvalid_m1       (bvalid_axi_m_1),
        .bready_m1       (bready_axi_m_1),  

        // Read Address Channel
        .aruser_m1       (aruseri_axi_m_1),
        .arid_m1         (arid_axi_m_1),
        .araddr_m1       (araddr_axi_m_1),
        .arlen_m1        (arlen_axi_m_1),
        .arsize_m1       (arsize_axi_m_1),
        .arburst_m1      (arburst_axi_m_1),
        .arlock_m1       (arlock_axi_m_1),
        .arcache_m1      (arcache_axi_m_1),
        .arprot_m1       (arprot_axi_m_1),
        .arvalid_m1      (arvalid_axi_m_1),
        .arvalid_vect_m1 (arvalid_vect_axi_m_1),
        .arready_m1      (arready_axi_m_1),
        .ar_qv_m1        (ar_qv_axi_m_1),
   
        // Read Channel
        .rid_m1          (rid_axi_m_1),
        .rdata_m1        (rdata_axi_m_1),
        .rresp_m1        (rresp_axi_m_1),
        .rlast_m1        (rlast_axi_m_1),
        .rvalid_m1       (rvalid_axi_m_1),
        .rready_m1       (rready_axi_m_1),

        // MasterInterface 2 (connects to Slave axi_m_5)
        // Write Address Channel
        .awuser_m2       (awuseri_axi_m_5),
        .awid_m2         (awid_axi_m_5),
        .awaddr_m2       (awaddr_axi_m_5),
        .awlen_m2        (awlen_axi_m_5),
        .awsize_m2       (awsize_axi_m_5),
        .awburst_m2      (awburst_axi_m_5),
        .awlock_m2       (awlock_axi_m_5),
        .awcache_m2      (awcache_axi_m_5),
        .awprot_m2       (awprot_axi_m_5),
        .awvalid_m2      (awvalid_axi_m_5),
        .awvalid_vect_m2 (awvalid_vect_axi_m_5),
        .awready_m2      (awready_axi_m_5),
        .aw_qv_m2        (aw_qv_axi_m_5),
   
        // Write Channel
        .wdata_m2        (wdata_axi_m_5),
        .wstrb_m2        (wstrb_axi_m_5),   
        .wlast_m2        (wlast_axi_m_5),
        .wvalid_m2       (wvalid_axi_m_5),
        .wready_m2       (wready_axi_m_5),

        // Write Response Channel
        .bid_m2          (bid_axi_m_5),
        .bresp_m2        (bresp_axi_m_5),
        .bvalid_m2       (bvalid_axi_m_5),
        .bready_m2       (bready_axi_m_5),  

        // Read Address Channel
        .aruser_m2       (aruseri_axi_m_5),
        .arid_m2         (arid_axi_m_5),
        .araddr_m2       (araddr_axi_m_5),
        .arlen_m2        (arlen_axi_m_5),
        .arsize_m2       (arsize_axi_m_5),
        .arburst_m2      (arburst_axi_m_5),
        .arlock_m2       (arlock_axi_m_5),
        .arcache_m2      (arcache_axi_m_5),
        .arprot_m2       (arprot_axi_m_5),
        .arvalid_m2      (arvalid_axi_m_5),
        .arvalid_vect_m2 (arvalid_vect_axi_m_5),
        .arready_m2      (arready_axi_m_5),
        .ar_qv_m2        (ar_qv_axi_m_5),
   
        // Read Channel
        .rid_m2          (rid_axi_m_5),
        .rdata_m2        (rdata_axi_m_5),
        .rresp_m2        (rresp_axi_m_5),
        .rlast_m2        (rlast_axi_m_5),
        .rvalid_m2       (rvalid_axi_m_5),
        .rready_m2       (rready_axi_m_5),

        // MasterInterface 3 (connects to Slave axi_m_6)
        // Write Address Channel
        .awuser_m3       (awuseri_axi_m_6),
        .awid_m3         (awid_axi_m_6),
        .awaddr_m3       (awaddr_axi_m_6),
        .awlen_m3        (awlen_axi_m_6),
        .awsize_m3       (awsize_axi_m_6),
        .awburst_m3      (awburst_axi_m_6),
        .awlock_m3       (awlock_axi_m_6),
        .awcache_m3      (awcache_axi_m_6),
        .awprot_m3       (awprot_axi_m_6),
        .awvalid_m3      (awvalid_axi_m_6),
        .awvalid_vect_m3 (awvalid_vect_axi_m_6),
        .awready_m3      (awready_axi_m_6),
        .aw_qv_m3        (aw_qv_axi_m_6),
   
        // Write Channel
        .wdata_m3        (wdata_axi_m_6),
        .wstrb_m3        (wstrb_axi_m_6),   
        .wlast_m3        (wlast_axi_m_6),
        .wvalid_m3       (wvalid_axi_m_6),
        .wready_m3       (wready_axi_m_6),

        // Write Response Channel
        .bid_m3          (bid_axi_m_6),
        .bresp_m3        (bresp_axi_m_6),
        .bvalid_m3       (bvalid_axi_m_6),
        .bready_m3       (bready_axi_m_6),  

        // Read Address Channel
        .aruser_m3       (aruseri_axi_m_6),
        .arid_m3         (arid_axi_m_6),
        .araddr_m3       (araddr_axi_m_6),
        .arlen_m3        (arlen_axi_m_6),
        .arsize_m3       (arsize_axi_m_6),
        .arburst_m3      (arburst_axi_m_6),
        .arlock_m3       (arlock_axi_m_6),
        .arcache_m3      (arcache_axi_m_6),
        .arprot_m3       (arprot_axi_m_6),
        .arvalid_m3      (arvalid_axi_m_6),
        .arvalid_vect_m3 (arvalid_vect_axi_m_6),
        .arready_m3      (arready_axi_m_6),
        .ar_qv_m3        (ar_qv_axi_m_6),
   
        // Read Channel
        .rid_m3          (rid_axi_m_6),
        .rdata_m3        (rdata_axi_m_6),
        .rresp_m3        (rresp_axi_m_6),
        .rlast_m3        (rlast_axi_m_6),
        .rvalid_m3       (rvalid_axi_m_6),
        .rready_m3       (rready_axi_m_6),

        // MasterInterface 4 (connects to Slave axi_m_7)
        // Write Address Channel
        .awuser_m4       (awuseri_axi_m_7),
        .awid_m4         (awid_axi_m_7),
        .awaddr_m4       (awaddr_axi_m_7),
        .awlen_m4        (awlen_axi_m_7),
        .awsize_m4       (awsize_axi_m_7),
        .awburst_m4      (awburst_axi_m_7),
        .awlock_m4       (awlock_axi_m_7),
        .awcache_m4      (awcache_axi_m_7),
        .awprot_m4       (awprot_axi_m_7),
        .awvalid_m4      (awvalid_axi_m_7),
        .awvalid_vect_m4 (awvalid_vect_axi_m_7),
        .awready_m4      (awready_axi_m_7),
        .aw_qv_m4        (aw_qv_axi_m_7),
   
        // Write Channel
        .wdata_m4        (wdata_axi_m_7),
        .wstrb_m4        (wstrb_axi_m_7),   
        .wlast_m4        (wlast_axi_m_7),
        .wvalid_m4       (wvalid_axi_m_7),
        .wready_m4       (wready_axi_m_7),

        // Write Response Channel
        .bid_m4          (bid_axi_m_7),
        .bresp_m4        (bresp_axi_m_7),
        .bvalid_m4       (bvalid_axi_m_7),
        .bready_m4       (bready_axi_m_7),  

        // Read Address Channel
        .aruser_m4       (aruseri_axi_m_7),
        .arid_m4         (arid_axi_m_7),
        .araddr_m4       (araddr_axi_m_7),
        .arlen_m4        (arlen_axi_m_7),
        .arsize_m4       (arsize_axi_m_7),
        .arburst_m4      (arburst_axi_m_7),
        .arlock_m4       (arlock_axi_m_7),
        .arcache_m4      (arcache_axi_m_7),
        .arprot_m4       (arprot_axi_m_7),
        .arvalid_m4      (arvalid_axi_m_7),
        .arvalid_vect_m4 (arvalid_vect_axi_m_7),
        .arready_m4      (arready_axi_m_7),
        .ar_qv_m4        (ar_qv_axi_m_7),
   
        // Read Channel
        .rid_m4          (rid_axi_m_7),
        .rdata_m4        (rdata_axi_m_7),
        .rresp_m4        (rresp_axi_m_7),
        .rlast_m4        (rlast_axi_m_7),
        .rvalid_m4       (rvalid_axi_m_7),
        .rready_m4       (rready_axi_m_7),

        // MasterInterface 5 (connects to Slave axi_m_8)
        // Write Address Channel
        .awuser_m5       (awuseri_axi_m_8),
        .awid_m5         (awid_axi_m_8),
        .awaddr_m5       (awaddr_axi_m_8),
        .awlen_m5        (awlen_axi_m_8),
        .awsize_m5       (awsize_axi_m_8),
        .awburst_m5      (awburst_axi_m_8),
        .awlock_m5       (awlock_axi_m_8),
        .awcache_m5      (awcache_axi_m_8),
        .awprot_m5       (awprot_axi_m_8),
        .awvalid_m5      (awvalid_axi_m_8),
        .awvalid_vect_m5 (awvalid_vect_axi_m_8),
        .awready_m5      (awready_axi_m_8),
        .aw_qv_m5        (aw_qv_axi_m_8),
   
        // Write Channel
        .wdata_m5        (wdata_axi_m_8),
        .wstrb_m5        (wstrb_axi_m_8),   
        .wlast_m5        (wlast_axi_m_8),
        .wvalid_m5       (wvalid_axi_m_8),
        .wready_m5       (wready_axi_m_8),

        // Write Response Channel
        .bid_m5          (bid_axi_m_8),
        .bresp_m5        (bresp_axi_m_8),
        .bvalid_m5       (bvalid_axi_m_8),
        .bready_m5       (bready_axi_m_8),  

        // Read Address Channel
        .aruser_m5       (aruseri_axi_m_8),
        .arid_m5         (arid_axi_m_8),
        .araddr_m5       (araddr_axi_m_8),
        .arlen_m5        (arlen_axi_m_8),
        .arsize_m5       (arsize_axi_m_8),
        .arburst_m5      (arburst_axi_m_8),
        .arlock_m5       (arlock_axi_m_8),
        .arcache_m5      (arcache_axi_m_8),
        .arprot_m5       (arprot_axi_m_8),
        .arvalid_m5      (arvalid_axi_m_8),
        .arvalid_vect_m5 (arvalid_vect_axi_m_8),
        .arready_m5      (arready_axi_m_8),
        .ar_qv_m5        (ar_qv_axi_m_8),
   
        // Read Channel
        .rid_m5          (rid_axi_m_8),
        .rdata_m5        (rdata_axi_m_8),
        .rresp_m5        (rresp_axi_m_8),
        .rlast_m5        (rlast_axi_m_8),
        .rvalid_m5       (rvalid_axi_m_8),
        .rready_m5       (rready_axi_m_8),

        // MasterInterface 6 (connects to Slave axi_m_9)
        // Write Address Channel
        .awuser_m6       (awuseri_axi_m_9),
        .awid_m6         (awid_axi_m_9),
        .awaddr_m6       (awaddr_axi_m_9),
        .awlen_m6        (awlen_axi_m_9),
        .awsize_m6       (awsize_axi_m_9),
        .awburst_m6      (awburst_axi_m_9),
        .awlock_m6       (awlock_axi_m_9),
        .awcache_m6      (awcache_axi_m_9),
        .awprot_m6       (awprot_axi_m_9),
        .awvalid_m6      (awvalid_axi_m_9),
        .awvalid_vect_m6 (awvalid_vect_axi_m_9),
        .awready_m6      (awready_axi_m_9),
        .aw_qv_m6        (aw_qv_axi_m_9),
   
        // Write Channel
        .wdata_m6        (wdata_axi_m_9),
        .wstrb_m6        (wstrb_axi_m_9),   
        .wlast_m6        (wlast_axi_m_9),
        .wvalid_m6       (wvalid_axi_m_9),
        .wready_m6       (wready_axi_m_9),

        // Write Response Channel
        .bid_m6          (bid_axi_m_9),
        .bresp_m6        (bresp_axi_m_9),
        .bvalid_m6       (bvalid_axi_m_9),
        .bready_m6       (bready_axi_m_9),  

        // Read Address Channel
        .aruser_m6       (aruseri_axi_m_9),
        .arid_m6         (arid_axi_m_9),
        .araddr_m6       (araddr_axi_m_9),
        .arlen_m6        (arlen_axi_m_9),
        .arsize_m6       (arsize_axi_m_9),
        .arburst_m6      (arburst_axi_m_9),
        .arlock_m6       (arlock_axi_m_9),
        .arcache_m6      (arcache_axi_m_9),
        .arprot_m6       (arprot_axi_m_9),
        .arvalid_m6      (arvalid_axi_m_9),
        .arvalid_vect_m6 (arvalid_vect_axi_m_9),
        .arready_m6      (arready_axi_m_9),
        .ar_qv_m6        (ar_qv_axi_m_9),
   
        // Read Channel
        .rid_m6          (rid_axi_m_9),
        .rdata_m6        (rdata_axi_m_9),
        .rresp_m6        (rresp_axi_m_9),
        .rlast_m6        (rlast_axi_m_9),
        .rvalid_m6       (rvalid_axi_m_9),
        .rready_m6       (rready_axi_m_9),

        // MasterInterface 7 (connects to Slave axi_m_4)
        // Write Address Channel
        .awuser_m7       (awuseri_axi_m_4),
        .awid_m7         (awid_axi_m_4),
        .awaddr_m7       (awaddr_axi_m_4),
        .awlen_m7        (awlen_axi_m_4),
        .awsize_m7       (awsize_axi_m_4),
        .awburst_m7      (awburst_axi_m_4),
        .awlock_m7       (awlock_axi_m_4),
        .awcache_m7      (awcache_axi_m_4),
        .awprot_m7       (awprot_axi_m_4),
        .awvalid_m7      (awvalid_axi_m_4),
        .awvalid_vect_m7 (awvalid_vect_axi_m_4),
        .awready_m7      (awready_axi_m_4),
        .aw_qv_m7        (aw_qv_axi_m_4),
   
        // Write Channel
        .wdata_m7        (wdata_axi_m_4),
        .wstrb_m7        (wstrb_axi_m_4),   
        .wlast_m7        (wlast_axi_m_4),
        .wvalid_m7       (wvalid_axi_m_4),
        .wready_m7       (wready_axi_m_4),

        // Write Response Channel
        .bid_m7          (bid_axi_m_4),
        .bresp_m7        (bresp_axi_m_4),
        .bvalid_m7       (bvalid_axi_m_4),
        .bready_m7       (bready_axi_m_4),  

        // Read Address Channel
        .aruser_m7       (aruseri_axi_m_4),
        .arid_m7         (arid_axi_m_4),
        .araddr_m7       (araddr_axi_m_4),
        .arlen_m7        (arlen_axi_m_4),
        .arsize_m7       (arsize_axi_m_4),
        .arburst_m7      (arburst_axi_m_4),
        .arlock_m7       (arlock_axi_m_4),
        .arcache_m7      (arcache_axi_m_4),
        .arprot_m7       (arprot_axi_m_4),
        .arvalid_m7      (arvalid_axi_m_4),
        .arvalid_vect_m7 (arvalid_vect_axi_m_4),
        .arready_m7      (arready_axi_m_4),
        .ar_qv_m7        (ar_qv_axi_m_4),
   
        // Read Channel
        .rid_m7          (rid_axi_m_4),
        .rdata_m7        (rdata_axi_m_4),
        .rresp_m7        (rresp_axi_m_4),
        .rlast_m7        (rlast_axi_m_4),
        .rvalid_m7       (rvalid_axi_m_4),
        .rready_m7       (rready_axi_m_4),

        // MasterInterface 8 (connects to Slave axi_m_2)
        // Write Address Channel
        .awuser_m8       (awuseri_axi_m_2),
        .awid_m8         (awid_axi_m_2),
        .awaddr_m8       (awaddr_axi_m_2),
        .awlen_m8        (awlen_axi_m_2),
        .awsize_m8       (awsize_axi_m_2),
        .awburst_m8      (awburst_axi_m_2),
        .awlock_m8       (awlock_axi_m_2),
        .awcache_m8      (awcache_axi_m_2),
        .awprot_m8       (awprot_axi_m_2),
        .awvalid_m8      (awvalid_axi_m_2),
        .awvalid_vect_m8 (awvalid_vect_axi_m_2),
        .awready_m8      (awready_axi_m_2),
        .aw_qv_m8        (aw_qv_axi_m_2),
   
        // Write Channel
        .wdata_m8        (wdata_axi_m_2),
        .wstrb_m8        (wstrb_axi_m_2),   
        .wlast_m8        (wlast_axi_m_2),
        .wvalid_m8       (wvalid_axi_m_2),
        .wready_m8       (wready_axi_m_2),

        // Write Response Channel
        .bid_m8          (bid_axi_m_2),
        .bresp_m8        (bresp_axi_m_2),
        .bvalid_m8       (bvalid_axi_m_2),
        .bready_m8       (bready_axi_m_2),  

        // Read Address Channel
        .aruser_m8       (aruseri_axi_m_2),
        .arid_m8         (arid_axi_m_2),
        .araddr_m8       (araddr_axi_m_2),
        .arlen_m8        (arlen_axi_m_2),
        .arsize_m8       (arsize_axi_m_2),
        .arburst_m8      (arburst_axi_m_2),
        .arlock_m8       (arlock_axi_m_2),
        .arcache_m8      (arcache_axi_m_2),
        .arprot_m8       (arprot_axi_m_2),
        .arvalid_m8      (arvalid_axi_m_2),
        .arvalid_vect_m8 (arvalid_vect_axi_m_2),
        .arready_m8      (arready_axi_m_2),
        .ar_qv_m8        (ar_qv_axi_m_2),
   
        // Read Channel
        .rid_m8          (rid_axi_m_2),
        .rdata_m8        (rdata_axi_m_2),
        .rresp_m8        (rresp_axi_m_2),
        .rlast_m8        (rlast_axi_m_2),
        .rvalid_m8       (rvalid_axi_m_2),
        .rready_m8       (rready_axi_m_2),


        // Internal AXI Connections 

        // Connects SlaveInterface 0  to Master Interface 0)

        // Write Address Channel
        .awuser_0_0       (awuser_0_0),
        .awid_0_0         (awid_0_0),
        .awaddr_0_0       (awaddr_0_0),
        .awlen_0_0        (awlen_0_0),
        .awsize_0_0       (awsize_0_0),
        .awburst_0_0      (awburst_0_0),
        .awlock_0_0       (awlock_0_0),
        .awcache_0_0      (awcache_0_0),
        .awprot_0_0       (awprot_0_0),
        .awvalid_0_0      (awvalid_0_0),
        .awvalid_vect_0_0 (awvalid_vect_0_0),
        .awready_0_0      (awready_0_0),
        .aw_qv_0_0        (aw_qv_0_0),
   
        // Write Channel
        .wdata_0_0        (wdata_0_0),
        .wstrb_0_0        (wstrb_0_0),   
        .wlast_0_0        (wlast_0_0),
        .wvalid_0_0       (wvalid_0_0),
        .wready_0_0       (wready_0_0),

        // Write Response Channel
        .bid_0_0          (bid_0_0),
        .bresp_0_0        (bresp_0_0),
        .bvalid_0_0       (bvalid_0_0),
        .bready_0_0       (bready_0_0),  

        // Read Address Channel
        .aruser_0_0       (aruser_0_0),
        .arid_0_0         (arid_0_0),
        .araddr_0_0       (araddr_0_0),
        .arlen_0_0        (arlen_0_0),
        .arsize_0_0       (arsize_0_0),
        .arburst_0_0      (arburst_0_0),
        .arlock_0_0       (arlock_0_0),
        .arcache_0_0      (arcache_0_0),
        .arprot_0_0       (arprot_0_0),
        .arvalid_0_0      (arvalid_0_0),
        .arvalid_vect_0_0 (arvalid_vect_0_0),
        .arready_0_0      (arready_0_0),
        .ar_qv_0_0        (ar_qv_0_0),
   
        // Read Channel
        .rid_0_0          (rid_0_0),
        .rdata_0_0        (rdata_0_0),
        .rresp_0_0        (rresp_0_0),
        .rlast_0_0        (rlast_0_0),
        .rvalid_0_0       (rvalid_0_0),
        .rready_0_0       (rready_0_0),


        // Connects SlaveInterface 0  to Master Interface 1)

        // Write Address Channel
        .awuser_0_1       (awuser_0_1),
        .awid_0_1         (awid_0_1),
        .awaddr_0_1       (awaddr_0_1),
        .awlen_0_1        (awlen_0_1),
        .awsize_0_1       (awsize_0_1),
        .awburst_0_1      (awburst_0_1),
        .awlock_0_1       (awlock_0_1),
        .awcache_0_1      (awcache_0_1),
        .awprot_0_1       (awprot_0_1),
        .awvalid_0_1      (awvalid_0_1),
        .awvalid_vect_0_1 (awvalid_vect_0_1),
        .awready_0_1      (awready_0_1),
        .aw_qv_0_1        (aw_qv_0_1),
   
        // Write Channel
        .wdata_0_1        (wdata_0_1),
        .wstrb_0_1        (wstrb_0_1),   
        .wlast_0_1        (wlast_0_1),
        .wvalid_0_1       (wvalid_0_1),
        .wready_0_1       (wready_0_1),

        // Write Response Channel
        .bid_0_1          (bid_0_1),
        .bresp_0_1        (bresp_0_1),
        .bvalid_0_1       (bvalid_0_1),
        .bready_0_1       (bready_0_1),  

        // Read Address Channel
        .aruser_0_1       (aruser_0_1),
        .arid_0_1         (arid_0_1),
        .araddr_0_1       (araddr_0_1),
        .arlen_0_1        (arlen_0_1),
        .arsize_0_1       (arsize_0_1),
        .arburst_0_1      (arburst_0_1),
        .arlock_0_1       (arlock_0_1),
        .arcache_0_1      (arcache_0_1),
        .arprot_0_1       (arprot_0_1),
        .arvalid_0_1      (arvalid_0_1),
        .arvalid_vect_0_1 (arvalid_vect_0_1),
        .arready_0_1      (arready_0_1),
        .ar_qv_0_1        (ar_qv_0_1),
   
        // Read Channel
        .rid_0_1          (rid_0_1),
        .rdata_0_1        (rdata_0_1),
        .rresp_0_1        (rresp_0_1),
        .rlast_0_1        (rlast_0_1),
        .rvalid_0_1       (rvalid_0_1),
        .rready_0_1       (rready_0_1),


        // Connects SlaveInterface 0  to Master Interface 2)

        // Write Address Channel
        .awuser_0_2       (awuser_0_2),
        .awid_0_2         (awid_0_2),
        .awaddr_0_2       (awaddr_0_2),
        .awlen_0_2        (awlen_0_2),
        .awsize_0_2       (awsize_0_2),
        .awburst_0_2      (awburst_0_2),
        .awlock_0_2       (awlock_0_2),
        .awcache_0_2      (awcache_0_2),
        .awprot_0_2       (awprot_0_2),
        .awvalid_0_2      (awvalid_0_2),
        .awvalid_vect_0_2 (awvalid_vect_0_2),
        .awready_0_2      (awready_0_2),
        .aw_qv_0_2        (aw_qv_0_2),
   
        // Write Channel
        .wdata_0_2        (wdata_0_2),
        .wstrb_0_2        (wstrb_0_2),   
        .wlast_0_2        (wlast_0_2),
        .wvalid_0_2       (wvalid_0_2),
        .wready_0_2       (wready_0_2),

        // Write Response Channel
        .bid_0_2          (bid_0_2),
        .bresp_0_2        (bresp_0_2),
        .bvalid_0_2       (bvalid_0_2),
        .bready_0_2       (bready_0_2),  

        // Read Address Channel
        .aruser_0_2       (aruser_0_2),
        .arid_0_2         (arid_0_2),
        .araddr_0_2       (araddr_0_2),
        .arlen_0_2        (arlen_0_2),
        .arsize_0_2       (arsize_0_2),
        .arburst_0_2      (arburst_0_2),
        .arlock_0_2       (arlock_0_2),
        .arcache_0_2      (arcache_0_2),
        .arprot_0_2       (arprot_0_2),
        .arvalid_0_2      (arvalid_0_2),
        .arvalid_vect_0_2 (arvalid_vect_0_2),
        .arready_0_2      (arready_0_2),
        .ar_qv_0_2        (ar_qv_0_2),
   
        // Read Channel
        .rid_0_2          (rid_0_2),
        .rdata_0_2        (rdata_0_2),
        .rresp_0_2        (rresp_0_2),
        .rlast_0_2        (rlast_0_2),
        .rvalid_0_2       (rvalid_0_2),
        .rready_0_2       (rready_0_2),


        // Connects SlaveInterface 0  to Master Interface 3)

        // Write Address Channel
        .awuser_0_3       (awuser_0_3),
        .awid_0_3         (awid_0_3),
        .awaddr_0_3       (awaddr_0_3),
        .awlen_0_3        (awlen_0_3),
        .awsize_0_3       (awsize_0_3),
        .awburst_0_3      (awburst_0_3),
        .awlock_0_3       (awlock_0_3),
        .awcache_0_3      (awcache_0_3),
        .awprot_0_3       (awprot_0_3),
        .awvalid_0_3      (awvalid_0_3),
        .awvalid_vect_0_3 (awvalid_vect_0_3),
        .awready_0_3      (awready_0_3),
        .aw_qv_0_3        (aw_qv_0_3),
   
        // Write Channel
        .wdata_0_3        (wdata_0_3),
        .wstrb_0_3        (wstrb_0_3),   
        .wlast_0_3        (wlast_0_3),
        .wvalid_0_3       (wvalid_0_3),
        .wready_0_3       (wready_0_3),

        // Write Response Channel
        .bid_0_3          (bid_0_3),
        .bresp_0_3        (bresp_0_3),
        .bvalid_0_3       (bvalid_0_3),
        .bready_0_3       (bready_0_3),  

        // Read Address Channel
        .aruser_0_3       (aruser_0_3),
        .arid_0_3         (arid_0_3),
        .araddr_0_3       (araddr_0_3),
        .arlen_0_3        (arlen_0_3),
        .arsize_0_3       (arsize_0_3),
        .arburst_0_3      (arburst_0_3),
        .arlock_0_3       (arlock_0_3),
        .arcache_0_3      (arcache_0_3),
        .arprot_0_3       (arprot_0_3),
        .arvalid_0_3      (arvalid_0_3),
        .arvalid_vect_0_3 (arvalid_vect_0_3),
        .arready_0_3      (arready_0_3),
        .ar_qv_0_3        (ar_qv_0_3),
   
        // Read Channel
        .rid_0_3          (rid_0_3),
        .rdata_0_3        (rdata_0_3),
        .rresp_0_3        (rresp_0_3),
        .rlast_0_3        (rlast_0_3),
        .rvalid_0_3       (rvalid_0_3),
        .rready_0_3       (rready_0_3),


        // Connects SlaveInterface 0  to Master Interface 4)

        // Write Address Channel
        .awuser_0_4       (awuser_0_4),
        .awid_0_4         (awid_0_4),
        .awaddr_0_4       (awaddr_0_4),
        .awlen_0_4        (awlen_0_4),
        .awsize_0_4       (awsize_0_4),
        .awburst_0_4      (awburst_0_4),
        .awlock_0_4       (awlock_0_4),
        .awcache_0_4      (awcache_0_4),
        .awprot_0_4       (awprot_0_4),
        .awvalid_0_4      (awvalid_0_4),
        .awvalid_vect_0_4 (awvalid_vect_0_4),
        .awready_0_4      (awready_0_4),
        .aw_qv_0_4        (aw_qv_0_4),
   
        // Write Channel
        .wdata_0_4        (wdata_0_4),
        .wstrb_0_4        (wstrb_0_4),   
        .wlast_0_4        (wlast_0_4),
        .wvalid_0_4       (wvalid_0_4),
        .wready_0_4       (wready_0_4),

        // Write Response Channel
        .bid_0_4          (bid_0_4),
        .bresp_0_4        (bresp_0_4),
        .bvalid_0_4       (bvalid_0_4),
        .bready_0_4       (bready_0_4),  

        // Read Address Channel
        .aruser_0_4       (aruser_0_4),
        .arid_0_4         (arid_0_4),
        .araddr_0_4       (araddr_0_4),
        .arlen_0_4        (arlen_0_4),
        .arsize_0_4       (arsize_0_4),
        .arburst_0_4      (arburst_0_4),
        .arlock_0_4       (arlock_0_4),
        .arcache_0_4      (arcache_0_4),
        .arprot_0_4       (arprot_0_4),
        .arvalid_0_4      (arvalid_0_4),
        .arvalid_vect_0_4 (arvalid_vect_0_4),
        .arready_0_4      (arready_0_4),
        .ar_qv_0_4        (ar_qv_0_4),
   
        // Read Channel
        .rid_0_4          (rid_0_4),
        .rdata_0_4        (rdata_0_4),
        .rresp_0_4        (rresp_0_4),
        .rlast_0_4        (rlast_0_4),
        .rvalid_0_4       (rvalid_0_4),
        .rready_0_4       (rready_0_4),


        // Connects SlaveInterface 0  to Master Interface 5)

        // Write Address Channel
        .awuser_0_5       (awuser_0_5),
        .awid_0_5         (awid_0_5),
        .awaddr_0_5       (awaddr_0_5),
        .awlen_0_5        (awlen_0_5),
        .awsize_0_5       (awsize_0_5),
        .awburst_0_5      (awburst_0_5),
        .awlock_0_5       (awlock_0_5),
        .awcache_0_5      (awcache_0_5),
        .awprot_0_5       (awprot_0_5),
        .awvalid_0_5      (awvalid_0_5),
        .awvalid_vect_0_5 (awvalid_vect_0_5),
        .awready_0_5      (awready_0_5),
        .aw_qv_0_5        (aw_qv_0_5),
   
        // Write Channel
        .wdata_0_5        (wdata_0_5),
        .wstrb_0_5        (wstrb_0_5),   
        .wlast_0_5        (wlast_0_5),
        .wvalid_0_5       (wvalid_0_5),
        .wready_0_5       (wready_0_5),

        // Write Response Channel
        .bid_0_5          (bid_0_5),
        .bresp_0_5        (bresp_0_5),
        .bvalid_0_5       (bvalid_0_5),
        .bready_0_5       (bready_0_5),  

        // Read Address Channel
        .aruser_0_5       (aruser_0_5),
        .arid_0_5         (arid_0_5),
        .araddr_0_5       (araddr_0_5),
        .arlen_0_5        (arlen_0_5),
        .arsize_0_5       (arsize_0_5),
        .arburst_0_5      (arburst_0_5),
        .arlock_0_5       (arlock_0_5),
        .arcache_0_5      (arcache_0_5),
        .arprot_0_5       (arprot_0_5),
        .arvalid_0_5      (arvalid_0_5),
        .arvalid_vect_0_5 (arvalid_vect_0_5),
        .arready_0_5      (arready_0_5),
        .ar_qv_0_5        (ar_qv_0_5),
   
        // Read Channel
        .rid_0_5          (rid_0_5),
        .rdata_0_5        (rdata_0_5),
        .rresp_0_5        (rresp_0_5),
        .rlast_0_5        (rlast_0_5),
        .rvalid_0_5       (rvalid_0_5),
        .rready_0_5       (rready_0_5),


        // Connects SlaveInterface 0  to Master Interface 6)

        // Write Address Channel
        .awuser_0_6       (awuser_0_6),
        .awid_0_6         (awid_0_6),
        .awaddr_0_6       (awaddr_0_6),
        .awlen_0_6        (awlen_0_6),
        .awsize_0_6       (awsize_0_6),
        .awburst_0_6      (awburst_0_6),
        .awlock_0_6       (awlock_0_6),
        .awcache_0_6      (awcache_0_6),
        .awprot_0_6       (awprot_0_6),
        .awvalid_0_6      (awvalid_0_6),
        .awvalid_vect_0_6 (awvalid_vect_0_6),
        .awready_0_6      (awready_0_6),
        .aw_qv_0_6        (aw_qv_0_6),
   
        // Write Channel
        .wdata_0_6        (wdata_0_6),
        .wstrb_0_6        (wstrb_0_6),   
        .wlast_0_6        (wlast_0_6),
        .wvalid_0_6       (wvalid_0_6),
        .wready_0_6       (wready_0_6),

        // Write Response Channel
        .bid_0_6          (bid_0_6),
        .bresp_0_6        (bresp_0_6),
        .bvalid_0_6       (bvalid_0_6),
        .bready_0_6       (bready_0_6),  

        // Read Address Channel
        .aruser_0_6       (aruser_0_6),
        .arid_0_6         (arid_0_6),
        .araddr_0_6       (araddr_0_6),
        .arlen_0_6        (arlen_0_6),
        .arsize_0_6       (arsize_0_6),
        .arburst_0_6      (arburst_0_6),
        .arlock_0_6       (arlock_0_6),
        .arcache_0_6      (arcache_0_6),
        .arprot_0_6       (arprot_0_6),
        .arvalid_0_6      (arvalid_0_6),
        .arvalid_vect_0_6 (arvalid_vect_0_6),
        .arready_0_6      (arready_0_6),
        .ar_qv_0_6        (ar_qv_0_6),
   
        // Read Channel
        .rid_0_6          (rid_0_6),
        .rdata_0_6        (rdata_0_6),
        .rresp_0_6        (rresp_0_6),
        .rlast_0_6        (rlast_0_6),
        .rvalid_0_6       (rvalid_0_6),
        .rready_0_6       (rready_0_6),


        // Connects SlaveInterface 0  to Master Interface 7)

        // Write Address Channel
        .awuser_0_7       (awuser_0_7),
        .awid_0_7         (awid_0_7),
        .awaddr_0_7       (awaddr_0_7),
        .awlen_0_7        (awlen_0_7),
        .awsize_0_7       (awsize_0_7),
        .awburst_0_7      (awburst_0_7),
        .awlock_0_7       (awlock_0_7),
        .awcache_0_7      (awcache_0_7),
        .awprot_0_7       (awprot_0_7),
        .awvalid_0_7      (awvalid_0_7),
        .awvalid_vect_0_7 (awvalid_vect_0_7),
        .awready_0_7      (awready_0_7),
        .aw_qv_0_7        (aw_qv_0_7),
   
        // Write Channel
        .wdata_0_7        (wdata_0_7),
        .wstrb_0_7        (wstrb_0_7),   
        .wlast_0_7        (wlast_0_7),
        .wvalid_0_7       (wvalid_0_7),
        .wready_0_7       (wready_0_7),

        // Write Response Channel
        .bid_0_7          (bid_0_7),
        .bresp_0_7        (bresp_0_7),
        .bvalid_0_7       (bvalid_0_7),
        .bready_0_7       (bready_0_7),  

        // Read Address Channel
        .aruser_0_7       (aruser_0_7),
        .arid_0_7         (arid_0_7),
        .araddr_0_7       (araddr_0_7),
        .arlen_0_7        (arlen_0_7),
        .arsize_0_7       (arsize_0_7),
        .arburst_0_7      (arburst_0_7),
        .arlock_0_7       (arlock_0_7),
        .arcache_0_7      (arcache_0_7),
        .arprot_0_7       (arprot_0_7),
        .arvalid_0_7      (arvalid_0_7),
        .arvalid_vect_0_7 (arvalid_vect_0_7),
        .arready_0_7      (arready_0_7),
        .ar_qv_0_7        (ar_qv_0_7),
   
        // Read Channel
        .rid_0_7          (rid_0_7),
        .rdata_0_7        (rdata_0_7),
        .rresp_0_7        (rresp_0_7),
        .rlast_0_7        (rlast_0_7),
        .rvalid_0_7       (rvalid_0_7),
        .rready_0_7       (rready_0_7),


        // Connects SlaveInterface 0  to Master Interface 8)

        // Write Address Channel
        .awuser_0_8       (awuser_0_8),
        .awid_0_8         (awid_0_8),
        .awaddr_0_8       (awaddr_0_8),
        .awlen_0_8        (awlen_0_8),
        .awsize_0_8       (awsize_0_8),
        .awburst_0_8      (awburst_0_8),
        .awlock_0_8       (awlock_0_8),
        .awcache_0_8      (awcache_0_8),
        .awprot_0_8       (awprot_0_8),
        .awvalid_0_8      (awvalid_0_8),
        .awvalid_vect_0_8 (awvalid_vect_0_8),
        .awready_0_8      (awready_0_8),
        .aw_qv_0_8        (aw_qv_0_8),
   
        // Write Channel
        .wdata_0_8        (wdata_0_8),
        .wstrb_0_8        (wstrb_0_8),   
        .wlast_0_8        (wlast_0_8),
        .wvalid_0_8       (wvalid_0_8),
        .wready_0_8       (wready_0_8),

        // Write Response Channel
        .bid_0_8          (bid_0_8),
        .bresp_0_8        (bresp_0_8),
        .bvalid_0_8       (bvalid_0_8),
        .bready_0_8       (bready_0_8),  

        // Read Address Channel
        .aruser_0_8       (aruser_0_8),
        .arid_0_8         (arid_0_8),
        .araddr_0_8       (araddr_0_8),
        .arlen_0_8        (arlen_0_8),
        .arsize_0_8       (arsize_0_8),
        .arburst_0_8      (arburst_0_8),
        .arlock_0_8       (arlock_0_8),
        .arcache_0_8      (arcache_0_8),
        .arprot_0_8       (arprot_0_8),
        .arvalid_0_8      (arvalid_0_8),
        .arvalid_vect_0_8 (arvalid_vect_0_8),
        .arready_0_8      (arready_0_8),
        .ar_qv_0_8        (ar_qv_0_8),
   
        // Read Channel
        .rid_0_8          (rid_0_8),
        .rdata_0_8        (rdata_0_8),
        .rresp_0_8        (rresp_0_8),
        .rlast_0_8        (rlast_0_8),
        .rvalid_0_8       (rvalid_0_8),
        .rready_0_8       (rready_0_8),


        // Connects SlaveInterface 1  to Master Interface 2)

        // Write Address Channel
        .awuser_1_2       (awuser_1_2),
        .awid_1_2         (awid_1_2),
        .awaddr_1_2       (awaddr_1_2),
        .awlen_1_2        (awlen_1_2),
        .awsize_1_2       (awsize_1_2),
        .awburst_1_2      (awburst_1_2),
        .awlock_1_2       (awlock_1_2),
        .awcache_1_2      (awcache_1_2),
        .awprot_1_2       (awprot_1_2),
        .awvalid_1_2      (awvalid_1_2),
        .awvalid_vect_1_2 (awvalid_vect_1_2),
        .awready_1_2      (awready_1_2),
        .aw_qv_1_2        (aw_qv_1_2),
   
        // Write Channel
        .wdata_1_2        (wdata_1_2),
        .wstrb_1_2        (wstrb_1_2),   
        .wlast_1_2        (wlast_1_2),
        .wvalid_1_2       (wvalid_1_2),
        .wready_1_2       (wready_1_2),

        // Write Response Channel
        .bid_1_2          (bid_1_2),
        .bresp_1_2        (bresp_1_2),
        .bvalid_1_2       (bvalid_1_2),
        .bready_1_2       (bready_1_2),  

        // Read Address Channel
        .aruser_1_2       (aruser_1_2),
        .arid_1_2         (arid_1_2),
        .araddr_1_2       (araddr_1_2),
        .arlen_1_2        (arlen_1_2),
        .arsize_1_2       (arsize_1_2),
        .arburst_1_2      (arburst_1_2),
        .arlock_1_2       (arlock_1_2),
        .arcache_1_2      (arcache_1_2),
        .arprot_1_2       (arprot_1_2),
        .arvalid_1_2      (arvalid_1_2),
        .arvalid_vect_1_2 (arvalid_vect_1_2),
        .arready_1_2      (arready_1_2),
        .ar_qv_1_2        (ar_qv_1_2),
   
        // Read Channel
        .rid_1_2          (rid_1_2),
        .rdata_1_2        (rdata_1_2),
        .rresp_1_2        (rresp_1_2),
        .rlast_1_2        (rlast_1_2),
        .rvalid_1_2       (rvalid_1_2),
        .rready_1_2       (rready_1_2),


        // Connects SlaveInterface 1  to Master Interface 3)

        // Write Address Channel
        .awuser_1_3       (awuser_1_3),
        .awid_1_3         (awid_1_3),
        .awaddr_1_3       (awaddr_1_3),
        .awlen_1_3        (awlen_1_3),
        .awsize_1_3       (awsize_1_3),
        .awburst_1_3      (awburst_1_3),
        .awlock_1_3       (awlock_1_3),
        .awcache_1_3      (awcache_1_3),
        .awprot_1_3       (awprot_1_3),
        .awvalid_1_3      (awvalid_1_3),
        .awvalid_vect_1_3 (awvalid_vect_1_3),
        .awready_1_3      (awready_1_3),
        .aw_qv_1_3        (aw_qv_1_3),
   
        // Write Channel
        .wdata_1_3        (wdata_1_3),
        .wstrb_1_3        (wstrb_1_3),   
        .wlast_1_3        (wlast_1_3),
        .wvalid_1_3       (wvalid_1_3),
        .wready_1_3       (wready_1_3),

        // Write Response Channel
        .bid_1_3          (bid_1_3),
        .bresp_1_3        (bresp_1_3),
        .bvalid_1_3       (bvalid_1_3),
        .bready_1_3       (bready_1_3),  

        // Read Address Channel
        .aruser_1_3       (aruser_1_3),
        .arid_1_3         (arid_1_3),
        .araddr_1_3       (araddr_1_3),
        .arlen_1_3        (arlen_1_3),
        .arsize_1_3       (arsize_1_3),
        .arburst_1_3      (arburst_1_3),
        .arlock_1_3       (arlock_1_3),
        .arcache_1_3      (arcache_1_3),
        .arprot_1_3       (arprot_1_3),
        .arvalid_1_3      (arvalid_1_3),
        .arvalid_vect_1_3 (arvalid_vect_1_3),
        .arready_1_3      (arready_1_3),
        .ar_qv_1_3        (ar_qv_1_3),
   
        // Read Channel
        .rid_1_3          (rid_1_3),
        .rdata_1_3        (rdata_1_3),
        .rresp_1_3        (rresp_1_3),
        .rlast_1_3        (rlast_1_3),
        .rvalid_1_3       (rvalid_1_3),
        .rready_1_3       (rready_1_3),


        // Connects SlaveInterface 1  to Master Interface 6)

        // Write Address Channel
        .awuser_1_6       (awuser_1_6),
        .awid_1_6         (awid_1_6),
        .awaddr_1_6       (awaddr_1_6),
        .awlen_1_6        (awlen_1_6),
        .awsize_1_6       (awsize_1_6),
        .awburst_1_6      (awburst_1_6),
        .awlock_1_6       (awlock_1_6),
        .awcache_1_6      (awcache_1_6),
        .awprot_1_6       (awprot_1_6),
        .awvalid_1_6      (awvalid_1_6),
        .awvalid_vect_1_6 (awvalid_vect_1_6),
        .awready_1_6      (awready_1_6),
        .aw_qv_1_6        (aw_qv_1_6),
   
        // Write Channel
        .wdata_1_6        (wdata_1_6),
        .wstrb_1_6        (wstrb_1_6),   
        .wlast_1_6        (wlast_1_6),
        .wvalid_1_6       (wvalid_1_6),
        .wready_1_6       (wready_1_6),

        // Write Response Channel
        .bid_1_6          (bid_1_6),
        .bresp_1_6        (bresp_1_6),
        .bvalid_1_6       (bvalid_1_6),
        .bready_1_6       (bready_1_6),  

        // Read Address Channel
        .aruser_1_6       (aruser_1_6),
        .arid_1_6         (arid_1_6),
        .araddr_1_6       (araddr_1_6),
        .arlen_1_6        (arlen_1_6),
        .arsize_1_6       (arsize_1_6),
        .arburst_1_6      (arburst_1_6),
        .arlock_1_6       (arlock_1_6),
        .arcache_1_6      (arcache_1_6),
        .arprot_1_6       (arprot_1_6),
        .arvalid_1_6      (arvalid_1_6),
        .arvalid_vect_1_6 (arvalid_vect_1_6),
        .arready_1_6      (arready_1_6),
        .ar_qv_1_6        (ar_qv_1_6),
   
        // Read Channel
        .rid_1_6          (rid_1_6),
        .rdata_1_6        (rdata_1_6),
        .rresp_1_6        (rresp_1_6),
        .rlast_1_6        (rlast_1_6),
        .rvalid_1_6       (rvalid_1_6),
        .rready_1_6       (rready_1_6),


        // Connects SlaveInterface 1  to Master Interface 8)

        // Write Address Channel
        .awuser_1_8       (awuser_1_8),
        .awid_1_8         (awid_1_8),
        .awaddr_1_8       (awaddr_1_8),
        .awlen_1_8        (awlen_1_8),
        .awsize_1_8       (awsize_1_8),
        .awburst_1_8      (awburst_1_8),
        .awlock_1_8       (awlock_1_8),
        .awcache_1_8      (awcache_1_8),
        .awprot_1_8       (awprot_1_8),
        .awvalid_1_8      (awvalid_1_8),
        .awvalid_vect_1_8 (awvalid_vect_1_8),
        .awready_1_8      (awready_1_8),
        .aw_qv_1_8        (aw_qv_1_8),
   
        // Write Channel
        .wdata_1_8        (wdata_1_8),
        .wstrb_1_8        (wstrb_1_8),   
        .wlast_1_8        (wlast_1_8),
        .wvalid_1_8       (wvalid_1_8),
        .wready_1_8       (wready_1_8),

        // Write Response Channel
        .bid_1_8          (bid_1_8),
        .bresp_1_8        (bresp_1_8),
        .bvalid_1_8       (bvalid_1_8),
        .bready_1_8       (bready_1_8),  

        // Read Address Channel
        .aruser_1_8       (aruser_1_8),
        .arid_1_8         (arid_1_8),
        .araddr_1_8       (araddr_1_8),
        .arlen_1_8        (arlen_1_8),
        .arsize_1_8       (arsize_1_8),
        .arburst_1_8      (arburst_1_8),
        .arlock_1_8       (arlock_1_8),
        .arcache_1_8      (arcache_1_8),
        .arprot_1_8       (arprot_1_8),
        .arvalid_1_8      (arvalid_1_8),
        .arvalid_vect_1_8 (arvalid_vect_1_8),
        .arready_1_8      (arready_1_8),
        .ar_qv_1_8        (ar_qv_1_8),
   
        // Read Channel
        .rid_1_8          (rid_1_8),
        .rdata_1_8        (rdata_1_8),
        .rresp_1_8        (rresp_1_8),
        .rlast_1_8        (rlast_1_8),
        .rvalid_1_8       (rvalid_1_8),
        .rready_1_8       (rready_1_8),


        // Miscelaneous connections
        .aclk    (aclk),
        .aresetn    (aresetn)
  );


  endmodule

//  --=============================== End ====================================--

